Other Parts Discussed in Thread: LM5141, LM5175
Some questions related the TDA4 EVM SOM schematics and layout.
1) We had the E5 schematics and noted that newer schematics are coming out very soon. We've been asked to identify, or at least outline what the changes are from “E5” to “E7” will be, what the affected circuits and function are?
2) On the Common Processor Board, we have several FLASH components, among them is a UFS device. What is the intent or use case for it?
3) it was noted that different supply information between the Common Processor Board power flow and power sequence diagrams on schematic pgs 5 and 6 (PROC079E2A) versus the notes within the schematic for the LM5175, LM5141, and LM5140.
4) Noted that the VDD_IO (SHV) voltage for the system is 3.3V, rather than 1.8V. What is the reason for this?
5) The SOM layout design is generating a number of uncommented DRC’s. We are wondering if these had been reviewed. We would like to understand what has been built and the impact and risk of those items that are reported.
