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AM5728: PCIe RC max payload size

Petr Buchta
Prodigy 120 points
Part Number: AM5728

Hello,

I'm using AM572x with Linux together with FPGA.

The PCIe RC reports Maximum Payload size for TLP 256 bytes, but is actually configured for 128B.  The FPGA reports 512B MaxPayload capability. This results in comunication using 128B TLP's.

How do I increase MaxPayload size on RC so the communication with FPGA is using 256B TLP's? Is there any device tree parametr I could use or any other way? Is it even possible or am I stuck with 128B TLP's?

Thank  you. 

  • 0
    TI__Guru**** 167971 points

    Hi,

    Can you please provide the output log of command "lspci -vv" on AM572x board?

  • 0 in reply to Bin Liu
    Prodigy 120 points

    00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01) (prog-if 00 [Normal decode])

    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+

    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

    Latency: 0, Cache Line Size: 64 bytes

    Interrupt: pin A routed to IRQ 372

    Region 0: Memory at 20100000 (32-bit, non-prefetchable) [size=1M]

    Region 1: Memory at 20020000 (32-bit, non-prefetchable) [size=64K]

    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0

    I/O behind bridge: None

    Memory behind bridge: 20200000-202fffff [size=1M]

    Prefetchable memory behind bridge: None

    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-

    BridgeCtl: Parity+ SERR- NoISA- VGA- VGA16- MAbort- >Reset- FastB2B-

    PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-

    Capabilities: [40] Power Management version 3

    Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)

    Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

    Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+

    Address: 00000000ae102000  Data: 0000

    Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00

    DevCap: MaxPayload 256 bytes, PhantFunc 0

    ExtTag- RBE+

    DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+

    RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+

    MaxPayload 128 bytes, MaxReadReq 512 bytes

    DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-

    LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <512ns, L1 <64us

    ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+

    LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk+

    ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

    LnkSta: Speed 5GT/s (ok), Width x1 (downgraded)

    TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+

    RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-

    RootCap: CRSVisible-

    RootSta: PME ReqID 0000, PMEStatus- PMEPending-

    DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-

    AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-

    DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-

    AtomicOpsCtl: ReqEn- EgressBlck-

    LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-

    Compliance De-emphasis: -6dB

    LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-

    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-

    Capabilities: [100 v2] Advanced Error Reporting

    UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

    UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

    UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-

    CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-

    CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+

    AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-

    MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-

    HeaderLog: 00000000 00000000 00000000 00000000

    RootCmd: CERptEn+ NFERptEn+ FERptEn+

    RootSta: CERcvd+ MultCERcvd+ UERcvd- MultUERcvd-

    FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0

    ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000

    Kernel driver in use: pcieport

    01:00.0 Serial controller: Xilinx Corporation Device 7021 (prog-if 01 [16450])

    Subsystem: Xilinx Corporation Device 0007

    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+

    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

    Latency: 0, Cache Line Size: 64 bytes

    Interrupt: pin A routed to IRQ 373

    Region 0: Memory at 20200000 (32-bit, non-prefetchable) [size=64K]

    Capabilities: [40] Power Management version 3

    Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)

    Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-

    Capabilities: [48] MSI: Enable+ Count=1/1 Maskable- 64bit+

    Address: 00000000ae102000  Data: 0001

    Capabilities: [60] Express (v2) Endpoint, MSI 00

    DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <64ns, L1 unlimited

    ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W

    DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-

    RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+

    MaxPayload 128 bytes, MaxReadReq 512 bytes

    DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-

    LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited

    ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-

    LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+

    ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

    LnkSta: Speed 5GT/s (ok), Width x1 (ok)

    TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

    DevCap2: Completion Timeout: Range B, TimeoutDis-, LTR-, OBFF Not Supported

    AtomicOpsCap: 32bit- 64bit- 128bitCAS-

    DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled

    AtomicOpsCtl: ReqEn-

    LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-

    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-

    Compliance De-emphasis: -6dB

    LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-

    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-

    Capabilities: [100 v1] Device Serial Number 00-00-00-00-00-00-00-00

    Kernel driver in use: xdma

    Kernel modules: xdma

  • 0 in reply to Petr Buchta
    TI__Guru**** 167971 points

    Hi,

    Please add the following option to your U-Boot bootargs parameter, it will set the the AM57x RC max payload to 256 bytes.

    "pci=pcie_bus_safe"

  • 0 in reply to Bin Liu
    Prodigy 120 points

    Thank you, that certainly did the trick. However, I'd expect increased throughput but the result is opposite. There is at least 25% drop when using 256B MPS. Could it relate to this - http://e2e.ti.com/support/processors/f/791/t/158004?