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DM365 hangs using EDMA (with ethernet)

Hi,

Shortly: an FPGA sends data over the AEMIF bus to the DM365. The DM365 hangs whenever this data is copied over from its original destination address to somewhere else in memory, but doesn't hang when it is just displayed on screen (that is a ssh console on the target).

I have an FPGA using the 16bit AEMIF bus to send data to the DM365. Whenever enough data is ready, it makes an edge on GPIO0.

On the linux side, I made a kernel module which uses the edma.h functions (I use DVSDK 3). The module gets the physical memory address of a buffer through CMEM and uses this as the destination of the DMA transfer. When a user-space request for FPGA data arrives at the kernel module through an IOCTL, here's what happens:

  • I configure the DMA channel (Ch 32) (source, destination, acnt, bcnt,...)
  • call edma_start
  • wait_for_completion(&ready)
  • return buffer's user space pointer

The DMA channel's ISR calls

  • edma_stop
  • complete(&ready)

This all works fine if I use the kernel in a program that just displays the buffer contents on the target device. The contents match the sent data, so I'm pretty confident functionally everything is ok.

However, when I use a simple server which pulls data out of the module and sends it to user space, there seems to be a hang caused by reading the buffer. I find this strange as I explicitly stop the edma (though GPIO edges still happen), so there should be nothing else accessing that memory space. When I configure the server to still pull the data from the module but send other (dummy) data to the client, there is no hang.

It really seems to be cause by copying the data to another memory, as I tried doing a simple memcpy on every received data-block in my testapp which does no client/server operations whatsoever.

I have been looking for a solution to this problem for many days now, and I ran out of ideas for a cause.

Help is highly appreaciated

Jasper

  • I believe I got the problem solved, but it seems it had nothing to do with my module architecture or anything in software: the FPGA was sending a stream of test data in which every word would have the maximum bitwise difference from the previous. i.e. it went from 0000 to FFFF to 0001 to FFFD and so on. 

    I am now of the assumption that this bus change is too much if it goes on for 76k words of 2 bytes. It involves massive switching on the DDR bus, and I managed to resolve the hanging by keeping the word semi-constant.

    I still have to investigate it more thoroughly, but until further notice, this problem is solved.