Hi,
My customers want to perform a PCIe compliance test on AM5746 custom board.
They want to output a specific bit pattern from the AM5746.
It is not a method to confirm by response from CLB.
* CLB is used only for waveform measurement
(Bit pattern K28.5-, D21.5, K28.5 +, D10.2)
We thought that the signal could be output by rewriting the following registers from ICE.
PCIECTRL_RC_DBICS_LNK_CAS_2
So we had questions.
1. Are there any PCIe projects that output the desired pattern?
AM5746 TI-RTOS pdk_am57xx_1_0_11
2. We want to test with the following settings. Would you tell me the procedure?
We thought of the following way.
(1) Set to Gen2 (5GT / s)
PCIECTRL_RC_DBICS_LNK_CAS_2: TRGT_LINK_SPEED
Write 0x2
(2) De-Emphasis setting (-3.5dB, -6dB)
PCIECTRL_RC_DBICS_LNK_CAS_2: COMPL_PRST_DEEPH
How can we set to -3.5dB and -6dB?
(3)Determination of test pattern
I want to output the following pattern.
* K28.5-, D21.5, K28.5 +, D10.2
Would you tell me the settings?
(4)Test pattern output (compliance test start)
PCIECTRL_RC_DBICS_LNK_CAS_2: ENTR_COMPL
Write 0x1
3. We can't understand the difference.
・PCIECTRL_RC_DBICS_LNK_CAS_2、
・PCIECTRL_RC_DBICS2_LNK_CAS_2
Which should we set? Would you tell me about the difference.