AM3358: MMC_CMD signal issue

Hi,

What is the card model? What software are you using? Which version?

Also, please post the MMC portion of the schematics.

Hi, Biser,

Can you please post the MMC portion of the schematics.

Hi, Biser,

Attached is the MMC0 section schematic. the AM3358 MMC0 is powered by 1.8V, so we add one 1.8V-3.3V SDIO signal level-translator chip TXS0108EPW

Hi, Biser,

We removed all external pull-up resistors before and after the SDIO level-translator chip, the result is the same.

What about the OE signal on the level translator? I see two resistors there. The one to GND should be removed.

Try also removing the ESD protection diodes on the AM335x side.

Hi, Biser,

The two resistors used in divider for OE pin are 1.2K and 10K, so the voltage at OE is low.

When the TVS are removed, the CMD16 can execute successfully. But the distortion still happens for a while after the CMD4 is executed.

So does this mean the distortion of CMD signal is just one temporary event after the MMC host switches to the new frequency (by CMD4 command)?

Below is section 4.3 of SD spec, describing that CMD4 can switch bus frequency.

Hi, Biser,

You are right that 1.2K resistor should be removed.

I didn't notice that the board I used was already rewoked to remove the 1.2K resistor. I just pasted the orignal schematic.

So, is the issue resolved?

Hi, Biser,

The CMD16 failure issue is resoved by removal of the TVS chips.

But the temporaty CMD signal distortion after CMD4 still exists. It would be better that TI can confirm this is normal during the initilization.

Thanks,

Can you post the PCB trace lengths from the processor to the voltage translator, and from the voltage translator to the card connector?

Hi, Biser,

I collected the following traces length information.

From processor to translator

CMD: 4995mil

CLK:  4826mil

From translator to TF connector

CMD: 1332 mil

CLK:  1331 mil

Hi,

I consulted this issue with a colleague. Here are his comments:

I suspect the delay through the level-translator is a much bigger problem than etch length.  Did you perform a timing analysis for the speed you are trying to operate taking into consideration all PCB trace delays and level-translator delays. You need to confirm that setup/hold timing requirements for each device, AM335x and card, are valid when including the PCB and level-translator delays.

Did you insert a series termination resistor (usually 22Ohm) on the clock signal near the source? If not, the loop-back clock topology used in AM335x could be susceptible to signal distortion and reflections on the clock signal.

Hi, Biser,

We removed the level-translator, and change the MMC0 working voltage to 3.3V and connect one standard SDIO memory card to the board, the same signal distortion happens after the CMD4.

And I think the signal distoriton after CMD4 is not related to SI. Since the clock and CMD signals have no distortion before CMD4. SI relates closely to the rise/fall edge, not the pulse frequency.

Can you check if that signal distortion is real? You are trying to capture a long sequence on the scope which required the time base to be slowed.  When the clock frequency increases, the scope is not sampling fast enough to properly resolve the signal.  The scope is capturing at a rate of 320ns per point, which is too slow for the faster signal rate.