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TDA4VM SOM Layout questions

Couple questions from one of my customers regarding the layout of the TDA4/J7 EVM:

  • There is a desire to avoid editing the high speed signals in the board layout, but it was noted that there are some uncommon callouts.  Single-ended (33, 40 and 66 ohm) and differential (66, 80, and 132 ohm) signals.  Here are some examples:
      • 33 ohm single-ended: LPDDR4_CAx nets on Layer 1 and Layer 7.  It’s also on the SI simulation coupon.
      • 40 ohm single-ended: LPDDR4_DQx nets on Layer 3 and Layer 5.  It’s also on the SI simulation coupon.
      • 66 ohm single-ended: LPDDR4_CAx nets on Layer 3.  It’s also on the SI simulation coupon.
      • DDR_CK diff pair appears to be 66 ohms differential on Layer 7, and 132 ohms differential on Layer 3.

Question 1:  Were these DDR signal callouts determined by simulation?

Question 2:  What material was used and is there a reference stackup doc from the manufacturer?  Since the fastest speeds in the design will likely be on CSI and PCIe (Gen 4) the customer wants to make sure that the materials will meet the speed requirements.


Thanks

John

  • Additional questions:

    1. There were a number of power domain changes in the design that are noted among the PMICs and to the SOC.  Did these fix issues during bring up, was power reduced, or were there an overstress or incorrect connection made?
    2. The customer is only able to generate 2 backdrill spans in the design.  One from Top side to layer 10 and another from Bottom side to layer 11.  There was a third backdrill span in the original TI design from Bottom side to layer 4.  We believe this one may be necessary as well, as it’s being used in the DDR region.  Can you please confirm this?
    3. Finally, there are 940 Drill Hole to Via Spacing errors and 114 Drill Hole to Drill Hole spacing errors in the TI E7 layout.  They are all related to backdrilling.  The drill hole to drill hole spacing is as low as ~3.6 mil in the DDR section.  The secondary drill (backdrill) diameter may be larger than necessary.  On an 8 mil finished hole (via) a secondary drill of 16-17 mil may be adequate.  The design is currently using a ~22 mil diameter secondary drill.  Is it possible to reduce this diameter?  Most of the DRC’s would likely be eliminated.

  • Yes - there we some power domain changes made from the initial design.  The changes all had do with fixing issues/and or incorrect connections.  No design improvements have been made to reduce power.

    For the TI EVM - we used back drilling for both SERDES and LPDDR4 interfaces.  For SERDES, back drill from TOP-10 to remove the via stub when transitioning from internal layer to bottom connector.  This is specific the EVM design, as the connectors are bottom of the board.  If connectors had been on top, back-drill would not be required.  The LPDDR4 uses two back-drills.  BOT-4 is used to remove the via stub a the command/address T-branch.  Back drill from BOT-L11 to remove stubs from most LPDDR4 signals (as they are routed on top-half of the PCB).  Both of these back drills showed in simulation to improve performance.

    Each PCB fab facility will have it own back drilling requirements - drill size,diameter, spacing, etc.

  • The uncommon impedances are mostly in the DDR region, and are a result of the T-branch topology required on the command/address signals.  The branch portion of the net should be two times the source net.  This can create some large impedance values, so effort was made to lower the impedances on the source nets.  33-ohms single ended, when branched becomes 66-ohms.  Yes - this values were simulated and shown to give good performance.

    As specified in the fab drawing of the EVM, the PCB material used was ISOLA I-speed.  The stackup is provided in the fab drawing.

  • Hi John,

    do you have any further questions on this? Can we close the thread?

    Regards,

    Yordan