Couple questions from one of my customers regarding the layout of the TDA4/J7 EVM:
- There is a desire to avoid editing the high speed signals in the board layout, but it was noted that there are some uncommon callouts. Single-ended (33, 40 and 66 ohm) and differential (66, 80, and 132 ohm) signals. Here are some examples:
- 33 ohm single-ended: LPDDR4_CAx nets on Layer 1 and Layer 7. It’s also on the SI simulation coupon.
- 40 ohm single-ended: LPDDR4_DQx nets on Layer 3 and Layer 5. It’s also on the SI simulation coupon.
- 66 ohm single-ended: LPDDR4_CAx nets on Layer 3. It’s also on the SI simulation coupon.
- DDR_CK diff pair appears to be 66 ohms differential on Layer 7, and 132 ohms differential on Layer 3.
Question 1: Were these DDR signal callouts determined by simulation?
Question 2: What material was used and is there a reference stackup doc from the manufacturer? Since the fastest speeds in the design will likely be on CSI and PCIe (Gen 4) the customer wants to make sure that the materials will meet the speed requirements.
Thanks
John