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TMS320C5517: McSPI usage

Kz777
Expert 7895 points

Part Number: TMS320C5517

Hi Champs,

1:Could you please  tell us how to reset McSPI_CLK bit count  automatically when assert McSPI_CS0 ?

2:When McSPI_CS0 became negate statement during data transmit , does C5000 has any trigger or flag ?

  For example,  some of other vendor MCU have "error interrupt " when CS0 negate during data transmit.

Regards,

Kz777

  • 0
    TI__Mastermind 30280 points

    Hi Kaz-san,

    I will have to get back to you on Monday after looking into these questions. Please stay tuned.

    Regards,
    Mark

  • 0 in reply to Mark M
    TI__Expert 7895 points

    Hi Mark,

    Thanks. I 'll wait your response.

  • 0 in reply to Kz777
    TI__Mastermind 30280 points

    Hi Kaz-san,

    I assume you are configuring McSPI for slave mode. I have checked the TRM, but I cannot find any interrupt or error flag to inform the system when the CS becomes inactive during a data transmission.


    See 9.4.4.2 Interrupt Events in Slave Mode:
    "In slave mode, the interrupt events related to the transmitter register state are TXx_EMPTY and TXx_UNDERFLOW. The interrupt events related to the receiver register state are RXx_FULL and RX0_OVERFLOW (Channels 1 and 2 do not have a receiver overflow status bit). See the IRQSTATUSL and IRQSTATUSU register."

    The TRM also reads... "When a McSPI word transfer completes (the CH0STATL[2:1] EOT and TXS bits set to 1), the received data is transferred to the channel receive register."
    Perhaps the EOT bit will not be set if the entire word is not shifted out before CS becomes inactive - try that experiment.

    "In slave mode, the McSPI initiates data transfer on the data lines (McSPI_SIMO and McSPI_SOMI) when it is selected by an active control signal (McSPI_CS0) and receives an SPI clock (McSPI_CLK) from the external SPI master device."

    "The transmitter register content is always loaded in the shift register whether it is updated or not. The event TX0_UNDERFLOW is activated accordingly and does not prevent transmission."

    Therefore, I believe the bit count should reset when McSPI detects the CS entering in the active state. Have you observed different behavior?

    Regards,
    Mark

  • 0 in reply to Mark M
    TI__Expert 7895 points

    Hi Mark,

    Thanks. I will check it .