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some questions about SPI of 6747

ma chenyang
Prodigy 100 points

     I have write some codes to use SPI of 6747.  I use SPI0 as the master and SPI1 as the slaver.   now I find  when  SPI0 send a data to SPI1  at the speed of 50MHZ. that'OK.

but when I try to use SPI1 send a data to SPI0 at 50MHZ..  the data is error...  I  slow the speed at 37.5MHZ.    data bocome right...

   I want to know  the 6747's speed of SPI  is linmited or not..  and why case this problom   thanks!!

  my code is very simple.

 Uint16 SPI0_RW_word(Uint16 data){

 Uint16 i;
while( SPI0_SPIBUF & 0x20000000 );

SPI0_SPIDAT1 = spidat1 | data;

while ( SPI0_SPIBUF & ( 0x80000000 ) );

 i=SPI0_SPIBUF;

 return i;

}

void SPI1_send_char(char data){
 while( SPI1_SPIBUF & 0x20000000 );
 SPI1_SPIDAT1 = data;
}

void main( void )
{
Uint32 i;
Uint16 j;
 /*初始化6747核*/
 C6747_init();

 SPI0_Configtion();
 SPI1_Configtion();
 for(;;){
 
  SPI1_send_char('a');
  j= SPI0_RW_word(0xff);

  if(j=='a'){
 
   printf("yes spi is ok");
   for(i=0;i<0xffff;i++);
  }
 else{
  printf("error!!!");
  for(i=0;i<0xffff;i++);

  }
 }

 

 

 

 

  • 0
    TI__Mastermind 27585 points

    Have you scoped the signal on the SPI1_SIMO to verify it is actually 50 MHz? SPI0 and SPI1 can run off of different PLLs so they may not be at the same frequency.

    Jeff

  • 0 in reply to jc-ti
    Prodigy 100 points

          I  have questions about what you said.   

          1:  you said that "SPI0 and SPI1  can run off of different PLLs"    ,but I see the data sheet  the clock of SPIs  is SYSCLK2 . I make SYSCLK2 is 150MHZ.  and set SPIs is SYSCLK2/3 . so SPIs  is 50MHZ.  

         2.SPI0 and SPI1 can run off of different PLLs . but I make SPI0 is the master and SPI1 is the slaver so when SPI1 try to send data to SPI0 .SPI1 should follow the clock of SPI0.. if I make SPI0 is 50MHZ.   should I care  the frequency of SPI1??

  • 0 in reply to ma chenyang
    TI__Mastermind 27585 points

    1) SPI1 can also run of PLL1. I dont know your PLL configuration so that was a possibility. Are they both sourced from PLL0?

    2) Thats true if SPI0 is always the master then it will always source the clock. You should check the signal integrity at the SPI0_SOMI pin. Does it look worse than the SPI1_SIMO pin? There may be an issue with one of the nets on your board that is limiting the bandwidth.

    Jeff