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RBL setting GPIO state

Jordan Dahl
Prodigy 70 points

A DM355 GPIO pin is being driven low on boot. This pin is being used to select the NAND device containing the UBL. It must be high to select the NAND device. I suspect that RBL is setting it low. Does anyone know exactly what RBL does to each PinMux, GPIOs, etc.?

Hardware configuration:
DM355 BTSEL[1:0]=00. AECFG[3:0]=1101.
SN74LVC138ARGYR decoder used to select NAND device:
SN74LVC138 pins [C,B,A] = DM355 pins {GIO[065], GIO[067], GIO[066]}

UBL NAND device chip select wired to SN74LVC138 \Y4, thus GIO065 must be high when booting to work properly. Instead it is currently getting [C,B,A] = 000, selecting \Y0. Obviously UBL doesn't load.

  • TI__Mastermind 37340 points

    To my knowledge, RBL does not support non-CE don't care NAND devices for NAND boot; this means that you can use NAND device with GPIO control of the CE, so long as is not used for booting purposes.

  • in reply to Juan Gonzales
    Prodigy 70 points

    I am doing a similar approach to the Spectrum Digital EVM. (See sheet 12 of 26 of their schematic). They use EM_CE0 and GIO066 (EM_A12) to decode the chip select two ways. I am decoding it several ways and so am using two more GIOs.

    At this point I simply want to know what GIOs the RBL messes with. It clearly works with GIO061 as the DM355 datasheet outlines. I am led to believe that it pulls GIO065 low. What else?