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TMS320C5515/05/14/04 Low-power CSL Macro Inaccuracies

Mike241
Intellectual 620 points
Other Parts Discussed in Thread: TMS320C5515

Some of the macro definitions in the CSL for the TMS320C5515 and related chips seem to be incorrect. 

The macros, mostly tokens, that I have found include the following

  • CSL_SYS_PRCR_<field>_RST_RST and _RST_NRST seem to have the wrong polarity.  (In cslr_sysctrl.h)

  • CSL_EMIF_ACS2CR2_SS_ENABLED and _DISABLED seem to have the wrong polarity.  (In cslr_emif.h)

There may be others.  If there are others and they are not going to be fixed in soon-to-be-released CSL versions, I'd like to know so I can account for them.  Does anyone have information on this?

Thanks.

 

 

 

  • 0
    TI__Mastermind 30140 points

    Hi Mike,

    I am going to look into these macro definitions tomorrow morning, but I just want to make sure you are using the latest (and greatest) CSL version: v2.10.00.00

    Thanks,
    Mark

     

  • 0 in reply to Mark M
    Intellectual 620 points

    Mark,

    Thanks for looking into it.  It looks like the CSL uses the values correctly.  The mnemonics are, however, a bit confusing.  See below for examples.

    • Setting a value of CSL_SYS_PRCR_PG4_RST_NRST puts the UART, SPI, etc. in reset, while reading a value of CSL_SYS_PRCR_PG4_RST_RST indicates that these peripherals are no longer in reset.
    • The value for CSL_EMIF_ACS2CR2_SS_ENABLED will enable Normal Mode while the value for CSL_EMIF_ACS2CR2_SS_DISABLED will enable Select Strobe mode.

    My recommendation would be to either provide clarification or change the mnemonics.  What are your thoughts?

  • 0 in reply to Mike241
    TI__Mastermind 30140 points

    Hi Mike,

    I see what you are talking about and I agree when you say the polarity is wrong:

    #define CSL_SYS_PRCR_<field>_RST_RST         (0x0000u)    //Sys User's Guide: Writing zero has no effect
    #define CSL_SYS_PRCR_<field>_RST_NRST        (0x0001u)    //Sys User's Guide: Writing one starts resetting the peripheral group

    So according to the System User's Guide RST_NRST actually starts resetting the peripherals. There are two instances in the CSL (csl_i2s.c & csl_spi.c) where the PRCR register is used to reset peripheral groups, but they use RST_NRST to initiate the reset. Misleading mnemonics, I agree.

    /*----SS Tokens----*/
    #define CSL_EMIF_ACS2CR2_SS_ENABLED      (0x0000u)    //EMIF User's Guide: Normal Mode enabled.
    #define CSL_EMIF_ACS2CR2_SS_DISABLED     (0x0001u)    //EMIF User's Guide: Select Strobe Mode enabled

    EMIF User's Guide: Select Strobe bit. This bit defines whether the asynchronous interface operates in Normal Mode or
    Select Strobe Mode. (1 Select Strobe Mode enabled.)

    Internal Documentation: ss - Select Strobe mode. Set to 1 if chip selects need to have write or read strobe timing (consistent with user's guide)

    According to the documentation, the Select Strobe bits are clearly backwards for all ACSnCR2 registers.

    This bit is not used by any CSL routine or example.

    I can submit these bugs to be fixed in the next CSL version, but there are possibly more instances of incorrect register bits. It could take a while to check each and every bit, but it needs to be done. I'll bring it up with the team.

    Thanks for this feedback. Let us know if you find any more inconsistencies.

    Regards,
    Mark

  • 0 in reply to Mark M
    TI__Mastermind 30140 points

    Mike,

    We will spend the time to double check every register and every bit in the CSLR definitions.

    For now, please modify your CSLR header files to fix these two bugs. That way when we update the CSL, you will not have to change your source code.

    You may also want to update csl_i2s.c & csl_spi.c accordingly, too.

    Thanks for bringing this to our attention.

    Best Regards,
    Mark

  • 0 in reply to Mark M
    Intellectual 620 points

    Thanks, Mark.