AM3354: NAND boot issue

Hi,

This is definitely not a ROM code or WDT issue. From your description it seems that the processor hangs somewhere in the initial bootloader read from NAND. Please post complete description of your use case - NAND type and geometry, NAND connections to AM335x, what is the software you are trying to boot, and which version, how id the NAND programmed, what ECC you are using.

Hi Biser,

Thanks a lot for quick response.

Let me collect the info you requested. In meantime, a couple of question regarding your reply:

1. Did you mean ROM boot stage "the processor hangs somewhere in the initial bootloader read from NAND?

2. What did you mean "how id the NAND programmed".

Our NAND device and connections with the processor:

1) NAND is MT29F1G08ABADAH4 from Micron,

2) Connections (n = LOW active)

NAND IO[7:0] to GPMC_AD[7:0]

NAND R_Bn to GPMC_WAIT0 (pin T17)

NAND WPn to GPMC_WPn (pin U17)

NAND ALE to GPMC_ADVN_ALE (pin R7)

NAND WEn to GPMC_WEn (pin U6)

NAND REn to GPMC_OEn_REn (pin T7)

NAND CEn to GPMC_CS0n (pin V6)

NAND CLE to GPMC_BE0n_CLE (pin T6)

boot-up-info.pdfboot-up-info.pdf

Hi Biser,

Have attached the boot-up info when it's OK. 

Hello,

I am wondering if you could please provide more information on the following items:

1. Are you able to replicate the same problem on multiple boards or just the current one?

2. I am wondering if it would be possible to probe the GPMC signals for any bus activity.

3. If the board does not boot, please connect to CCS and share the value of the control status register:

4. The hardware schematic you are currently using is based on what reference board design?

5. Since the issue is intermittent, are there any specific instances that triggers the board to not boot (like after board reset)?

Regards,
Krunal

Hi Krunal,

for answering your question:

1. yes, it happens on all boards randomly

2.have probed read, write etc. for example, seeing no differences boot-up or not boot-up

3. have not tried with debugger yet,

4. board design was based on one of TI eval board and associated component datasheets,

5. it is intermittent at power-on.

I have some questions,

(1) should the watchdog kick in about 3 minutes when not boot-up or not get into SPL/MLO stage? it should according to the TRM.

(2) according to TRM again, the routine that ROM code detecting the NAND is waiting 250ms for NAND ready, 200ms for reset or so (?) and then following by a couple runs of reset and reading ID etc.

should the watchdog kick to restart boot-sequence if not succeed? 

(3) if ROM code was failed from reading the NAND, should watchdog kick to restart the boot sequence? 

Hope to hear from you ASAP. Thank you.

Hi Biser,

Here are the info as per you requested:

[Biser] - NAND type and geometry:

The NAND Flash MT29F1G08ABADAH4

Organization

– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Device size: 1Gb: 1024 blocks

NAND connections to AM335x,

[Biser] - what is the software you are trying to boot, and which version,

SW version: Linux version 4.6.0 from our print-outs and display following by use CAT command:

NAME=Buildroot
VERSION=2018.08.2
ID=buildroot
VERSION_ID=2018.08.2
PRETTY_NAME="Buildroot 2018.08.2"

[Biser] - how id the NAND programmed,

Our programming coded that's modified from others

what ECC you are using.

BCH8 when programming NAD

Nevertheless, should or would watchdog kick to restart booting sequence if boot hangs or could not get into SPL/MLO stage? 

Hope to hear from YOU ASAP. Thanks.

Hello Krunal,

Any updates? Do you need more info from us?

Long story short, I like to confirm if the watchdog kicks to restart the boot-up sequence after 3 minutes when boot-up stuck (e.g. read NAND) as TRM stated? Thanks.

Hi Biser,

Any updates? Do you need more info from us?

Long story short, I like to confirm if the watchdog kicks to restart the boot-up sequence after 3 minutes when boot-up stuck (e.g. ROM or SPL/MLO trying to read NAND) as TRM stated? Thanks.

Hello,

In the above post, you mentioned "have probed read, write etc. for example, seeing no differences boot-up or not boot-up" and I am wondering if you are observing any bus activities. If yes, that means the problem is not related with WDT or ROM code as mentioned by Biser. 

Based on your working boot logs, you seem to be using Uboot 2018.07 and it is not supported by TI (we only support ti-u-boot-2018.01/ti-u-boot-2019.01)

Regards,
Krunal

Hi Krunal,

We observed bus activity every time power-on (e.g. probing read and write signals etc.). However it didn't boot-up sometimes and no print-out messages from hyper terminal (UART0). 

Did you mean it's in SPL or MLO stage but not ROM boot stage? So that the watchdog won't kick, would it? Thanks.

Hello,

Watchdog is enabled in the ROM code but disabled very early in the SPL stage. After the board fails to boot, please connect the CortexA8 processor using CCS (no gel files) and read the Program Counter (Registers Window). The SPL is executed in RAM and the start address for RAM is 0x402F_0400. Also, you should be seeing the warm reset signal toggle when the WD times out (ROM code).

Regards,
Krunal