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Original question:

Linux/AM3358: Ethernet not settling to 1GBPS

AM3358: Ethernet 1Gbps issue

MADHU GANDEPALLI
Expert 1300 points
Part Number: AM3358

Hello All,

This is in continuation with the https://e2e.ti.com/support/processors/f/791/t/822159.

My schematics are similar to the GP-EVM but board layout may vary. Is there any specific requirement in the Ethernet board layout to settle to 1GBPS?

Regards

Ma_hu

  • 0
    TI__Mastermind 27890 points

    Hello,

    As outlined in the previous thread, the link negotiation process occurs between the two PHYs. The MAC doesn't have any influence over this process, but instead simply responds to the commands from the PHY indicating the negotiated link conditions. The recommendation continues to be that you contact the PHY vendor for debug options.

    SPRAAR7 from TI.COM is a good reference for general layout considerations. There is nothing specific to RGMII, but all of the recommendations contained in this document would be applicable to most high-speed interfaces.

  • 0 in reply to -DK-
    Expert 1300 points

    Hello,

    I have tried to contact the PHY team but couldn't contact.

    But one of my PHY experts says , In Linux, kernel drivers are the ones who load the values into the registers and they may also be responsible for not settling to 1GBPs.

    If the driver doesn't load the values properly into the respective registers , then there are chances to this issue.

    His point is when the schematic is same as the eval board, how come the PHY come into picture in my board and also there are no board layout restrictions to achieve 1GBps. So hardware wise he claims that PHY is responding properly as he could see similar hardware with EVM and my board.

    Kindly comment on this.

    Regards

    Mad_hu.

  • 0 in reply to MADHU GANDEPALLI
    TI__Mastermind 27890 points

    Hi,

    As I mentioned earlier, the speed negotiation is handled 100% by the PHY's. There is no SW interaction at this layer of the OSI model.

    Also, it is not correct that there "are no layout restrictions" for enabling GigE. This is a high-speed interface and does require basic layout considerations as well as a timing analysis. That said, because the linking is done at the PHY level (again...no interaction from MAC), the portion of the board layout that would affect this is limited to the layout supporting the PHY. In the case of a poor board layout that affected the MAC, typically one would still link at the highest negotiated speed but would see errors on the MAC-side interface.

    You really do need help from the manufacturer of the PHY as there are diagnostic registers inside the PHY that can be read via the MDIO bus that can help debug the issue.