AM5728: Crossbar and INTC configuration

/*
 * Copyright (c) Texas Instruments, Inc 2016
 *
 * Authors:
 *  Vitaly Andrianov <vitalya@ti.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <ti/board/board.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/csl/soc.h>
#include <ti/csl/arch/a15/interrupt.h>
#include <ti/csl/csl_timer.h>

#define INTERVAL 1000 // 10 ms
#define RELOAD	 (0xffffffff - INTERVAL)
#define XBAR_CPU                        (CSL_XBAR_IRQ_CPU_ID_MPU)
#define XBAR_INST                       (CSL_XBAR_INST_MPU_IRQ_134)
#define XBAR_INST_ALTERNATE             (CSL_XBAR_INST_MPU_IRQ_130)
#define XBAR_INTR_SOURCE                (CSL_XBAR_TIMER8_IRQ)


#define TIMER8_IRQ_N (134 + 32)

struct timer_regs {
    volatile uint32_t   tidr;
    uint32_t        res1[3];
    volatile uint32_t   tiocp_cfg;
    uint32_t        res2[3];
    volatile uint32_t   irq_eoi;
    volatile uint32_t   irqstatus_raw;
    volatile uint32_t   irqstatus;
    volatile uint32_t   irqenable_set;
    volatile uint32_t   irqenable_clr;
    volatile uint32_t   irqwakeen;
    volatile uint32_t   tclr;
    volatile uint32_t   tcrr;
    volatile uint32_t   tldr;
    volatile uint32_t   ttgr;
    volatile uint32_t   twps;
    volatile uint32_t   tmap;
    volatile uint32_t   tcar1;
    volatile uint32_t   tsicr;
    volatile uint32_t   tcar2;
};


/*
 ** Crossbar Instance 5 does not allow crossbar input,
 ** instance 132 and 133 are not connected to INTC;
 ** therefore these three instances cannot be used
 */
static const int32_t intrA15[] = { 4, 7, 8, 9, -1, 11, 12, 13, 14, 15, 16, 17,
                                   18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
                                   29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
                                   40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
                                   51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
                                   62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
                                   73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
                                   84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94,
                                   95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
                                   105, 106, 107, 108, 109, 110, 111, 112, 113,
                                   114, 115, 116, 117, 118, 119, 120, 121, 122,
                                   123, 124, 125, 126, 127, 128, 129, 130, 133,
                                   134, 135, 136, 137, 138, -1, -1, 141, 142,
                                   143, 144, 145, 146, 147, 148, 149, 150, 151,
                                   152, 153, 154, 155, 156, 157, 158, 159 };




struct timer_regs *timer8 = (struct timer_regs *)CSL_MPU_TIMER8_REGS;

static volatile uint32_t reg_val;


static void myBoardInit(void);
static void INTCConfigure(uint32_t xbarInst);
static void inttest_mainloop(void);
static void myDelay(uint32_t val);

/**
 * main.c
 */
int main(void)
{
    myBoardInit();

    inttest_mainloop();
    return 0;
}


static void handle_IRQ(unsigned int irqn)
{
    static uint8_t ctr;
    timer8->irqstatus = 0x2; // mark IRQ as handled by clearing the flag
    if(ctr++ == 0) UART_puts("-",1);
}

static void myDelay(uint32_t val)
{
    int j, k;

    for (j = 0; j < val; j++){
        for (k = 0; k < 0x7fff; k++) {
            reg_val = HWREG(0x4a0098f8); // CM_L4SEC_SHA2MD52_CLKCTRL
        }
    }
}


void myBoardInit(void)
{
    Board_initCfg boardCfg;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
               BOARD_INIT_MODULE_CLOCK  |
               BOARD_INIT_UART_STDIO;

    Board_init(boardCfg);


    UART_puts("\nBoard initialized:\n", -1);
}


/*
 ** This function configures the INTC to receive UART interrupts.
 */
static void INTCConfigure(uint32_t xbarInst)
{

    CSL_xbarIrqConfigure(XBAR_CPU, xbarInst, XBAR_INTR_SOURCE);


    /* Registering the Interrupt Service Routine(ISR). */
    uint32_t intcNum = intrA15[xbarInst - 1];
    Intc_IntRegister(intcNum, (IntrFuncPtr) handle_IRQ,
                     (void*) XBAR_INTR_SOURCE);

    /* Setting the priority for the UART interrupt in INTC. */
    Intc_IntPrioritySet(intcNum, 1, 0);

    /* Enabling the UART interrupt in INTC. */
    Intc_SystemEnable(intcNum);
}

static void inttest_mainloop(void)
{
    uint32_t l;
    bool alternate_xbar_conf = false;
    myDelay(10);
    //uart_init();
    UART_printf("Hey, I'm working !!!!!!!!!!!\n\r");

    /* Initializing the Interrupt Controller. */
    Intc_Init();
    /* Enable the interrupt */
    Intc_IntEnable(0);

    myDelay(100);

    UART_printf("Configuring interrupt. xbar inst: %d(intcnum %d)\r\n", XBAR_INST, intrA15[XBAR_INST-1]);
    INTCConfigure(XBAR_INST);
    CSL_a15EnableCache();

    UART_printf("timer id ", timer8->tidr);
    timer8->tcrr = RELOAD;
    timer8->tldr = RELOAD;
    timer8->irqstatus = 0x2;
    l = timer8->tclr;
    l &= ~0x1c;
    l |= 0x23;
    timer8->tclr = l;

    timer8->irqenable_set = CSL_DMTIMER1MS_IRQSTATUS_SET_OVF_EN_FLAG_MASK;

    timer8->irqstatus = 0x2;
    uint16_t irq_fail = 0;
    for (;;)
    {
        // delay so long, that the IRQ flag is on for sure, if the IRQ is not working
        myDelay(100);

        // check the IRQ flag
        if(timer8->irqstatus & 0x02 || irq_fail > 5)
        {
            if(irq_fail <= 5)
            {
                // clear the IRQ flag
                timer8->irqstatus = 0x02;
                UART_printf("\r\nIRQ flag on - clearing IRQ\r\n");
            }
            irq_fail++;
            if(irq_fail > 5)
            {
                // after 5 subsequent fails, change the XBAR configuration.
                // The interrupt seems to work correctly after
                irq_fail  = 0;
                alternate_xbar_conf = !alternate_xbar_conf;
                uint32_t xbarInst = alternate_xbar_conf?XBAR_INST_ALTERNATE:XBAR_INST;
                UART_printf("\r\nReconfiguring interrupt. xbar inst: %d(intcnum %d)\r\n", xbarInst, intrA15[xbarInst-1]);
                INTCConfigure(xbarInst);
            }
        }
        else
        {
            if(alternate_xbar_conf)
            {
                // we don't want the alternate configuration, so increase the fail counter anyway.
                irq_fail++;
            }
            else
            {
                irq_fail = 0;
            }
        }
    }
}