DRA756: One slot data is missing in McASP I2S slave mode

Rajee Sankar

Part Number: DRA756

Linux kernel version: 7_04_00_03

Hi,

Our tuner is configured to McASP2 with below configurations. Issue is, we are getting only I data, no Q data. Q channel is always having garbage value like 4000 0000 4000 0000...

Tuner : Master mode

MCASP : slave mode

Data format: I2S (In davinci_set_dai_fmt() call, SND_SOC_DAIFMT_DSP_A is choosen with data_delay edited as zero. This DSP_A mode only giving the required FSRP and FRWID in RXFMT register)

Serializer: 0 (AXR0) in receive mode

Slot count : 2 (slot 0 and 1)

slot size: 32

Rx Rotate: 16 bits

Channels: 2

Active serializer and max active serializers: 1 (edited in davinci-mcasp.c file)

rx-num-evt: 8 (set as 8 in dts file, but this numevt hardcoded as 32 in davinci-mcasp.c file by default to correct the Errata i868)

And also please find the further mcasp register details.

1	RMASK	0xFFFFFFFF
	RFMT:
	RDATDLY	0 bit delay
	RRVRS	MSB first
	RPAD	0
	RPBIT	0
	RSSZ	slot size = 32
	RBUSEL	DATA port
	RROT	rotate 16 bits
	RXFMCTL:
	RMOD	2 slot TDM
	FRWID	single bit
	FSRM	external
	FSRP	rising edge
	ACLKRCTL:
	CLKRP	Falling
	CLKRM	external
	CLKRDIV	div by 1(default value)
	AHCLKRCTL:
	HCLKRP	Not inverted(default value)
	HCLKRM	internal(default value)
	HCLKRDIV	div by 1 (default value)
	RXTDM	3 (slot 0 and 1)
	ALSA word length	32

What goes wrong here? Please help us.

Regards,

Rajeswari S

over 7 years ago

0 Misael Lopez Cruz over 7 years ago

TI__Genius 9325 points

Do you have any diagram showing the audio frame sent by the tuner? Of interest are: frame size, slot size, bit clock polarity, frame sync duration and polarity.

Is I data sent on the first slot and Q data on the second slot?

Also if possible, please send the output of "omapconf show mcaspN" and "omapconf dump mcaspN" during the test.

In case you haven't used omapconf before, please download from here.

0 Rajee Sankar over 7 years ago in reply to Misael Lopez Cruz

Intellectual 295 points

Thank you for the reply Cruz!

Please find the attached tuner data format diagram.

#omapconf show mcasp2

OMAPCONF (rev 1.73-nogit built Fri Aug 30 11:12:40 IST 2019)

HW Platform:
Generic DRA74X (Flattened Device Tree)
DRA75X ES1.1 GP Device (STANDARD performance (1.5GHz))
TPS659038 ES2.0

SW Build Details:
Build:
    Version: _____                    _____           _         _
Kernel:
    Version: 3.14.63-00015-g7d1141e-dirty
    Toolchain: gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03)
    Type: #17 SMP PREEMPT
    Date: Fri Aug 30 12:43:16 IST 2019

|--------------------------------------------|
| Data Ports and Buffers                     |
|--------------------------------------------|
| Port                   | DATA bus          |
| Transmit DMA           |                   |
|   DMA request          | Enabled           |
|   Status               | No error          |
| Receive DMA            |                   |
|   DMA request          | Enabled           |
|   Status               | No error          |
| Transmit Buffer (XBUF) |                   |
|   Status               | No error          |
| Receive Buffer (RBUF) |                   |
|   Status               | No error          |
| Write FIFO (WFIFO)     |                   |
|   State                | Disabled          |
|   Threshold            | 16 samples        |
|   Level                | 0 samples in FIFO |
| Read FIFO (RFIFO)      |                   |
|   State                | Enabled           |
|   Threshold            | 32 samples        |
|   Level                | 2 samples in FIFO |
|--------------------------------------------|

|----------------------------------------|
| Control                                |
|----------------------------------------|
| Transmit State-Machine |               |
|   State                | Held in reset |
| Transmit Sequencer     |               |
|   Enabled Slots        | 2             |
|   Active Slots         | 2             |
|   Active Slots Mask    | 0x00000003    |
|   Current Slot         | Inactive      |
| Receive State-Machine |               |
|   State                | Active        |
| Receive Sequencer      |               |
|   Enabled Slots        | 2             |
|   Active Slots         | 2             |
|   Active Slots Mask    | 0x00000003    |
|   Current Slot         | 0             |
|----------------------------------------|

|-----------------------------------------------------|
| Clocks                                              |
|-----------------------------------------------------|
| Transmit Bit Clock        |                         |
|   State                   | Held in reset           |
|   Divider                 | Divide-by 1             |
|   Source                  | External (ACLKX pin)    |
|   Polarity                | Driven on rising edge   |
| Transmit High-Speed Clock |                         |
|   State                   | Held in reset           |
|   Divider                 | Divide-by 1             |
|   Source                  | Internal (AUXCLK)       |
|   Polarity                | Non-inverted            |
| Receive Bit Clock         |                         |
|   State                   | Running                 |
|   Divider                 | Divide-by 1             |
|   Source                  | External (ACLKR pin)    |
|   Polarity                | Samples on falling edge |
| Receive High-Speed Clock |                         |
|   State                   | Running                 |
|   Divider                 | Divide-by 1             |
|   Source                  | Internal (AUXCLK)       |
|   Polarity                | Non-inverted            |
| Sync Mode                 | Synchronous to TX       |
| Idle Mode                 | No-idle                 |
|-----------------------------------------------------|

|---------------------------------------------------|
| Frame Sync Generator                              |
|---------------------------------------------------|
| Transmit Frame Sync |                             |
|   Generator State   | Held in reset               |
|   Source            | External                    |
|   Polarity          | Frame starts on rising edge |
|   Pulse Width       | Single bit                  |
|   Slot Count        | 2 (TDM)                     |
|   Data Delay        | 0-bit                       |
|   Status            | No error                    |
| Receive Frame Sync |                             |
|   Generator State   | Active                      |
|   Source            | External                    |
|   Polarity          | Frame starts on rising edge |
|   Pulse Width       | Single bit                  |
|   Slot Count        | 2 (TDM)                     |
|   Data Delay        | 0-bit                       |
|   Status            | Unexpected frame sync       |
| Sync Mode           | Synchronous to TX           |
|---------------------------------------------------|

|-----------------------------------------|
| Format Units                            |
|-----------------------------------------|
| Transmit Format Unit |                  |
|   Slot Size          | 32 bits          |
|   Bit Mask           | 0xFFFFFFFF       |
|   Padding            | Pad with 0       |
|   Right-Rotation     | 0 bit positions |
|   Bitstream Order    | MSB first        |
| Receive Format Unit |                  |
|   Slot Size          | 32 bits          |
|   Bit Mask           | 0xFFFFFFFF       |
|   Padding            | Pad with 0       |
|   Right-Rotation     | 16 bit positions |
|   Bitstream Order    | MSB first        |
|-----------------------------------------|

|---------------------------------|
| Serializers                     |
|---------------------------------|
| Transmit Serializers | Cleared |
| Receive Serializers | Active   |
| Serializer 0         |          |
|   Mode               | Receive |
|   Inactive State     | Hi-Z     |
| Serializer 1         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 2         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 3         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 4         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 5         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 6         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 7         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 8         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 9         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 10        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 11        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 12        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 13        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 14        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 15        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
|---------------------------------|

|--------------------------------------------|
| Pin Control                                |
|--------------------------------------------|
| AFSR            |                          |
|   Functionality | Receive Frame Sync       |
|   Direction     | Input                    |
| ACLKR           |                          |
|   Functionality | Receive Bit Clock        |
|   Direction     | Input                    |
| AFSX            |                          |
|   Functionality | Transmit Frame Sync      |
|   Direction     | Input                    |
| ACLKX           |                          |
|   Functionality | Transmit Bit Clock       |
|   Direction     | Input                    |
| AHCLKX          |                          |
|   Functionality | Transmit High-Freq Clock |
|   Direction     | Input                    |
| AXR0            |                          |
|   Functionality | TX/RX Data Channel 0     |
|   Direction     | Input                    |
| AXR1            |                          |
|   Functionality | TX/RX Data Channel 1     |
|   Direction     | Input                    |
| AXR2            |                          |
|   Functionality | TX/RX Data Channel 2     |
|   Direction     | Input                    |
| AXR3            |                          |
|   Functionality | TX/RX Data Channel 3     |
|   Direction     | Input                    |
| AXR4            |                          |
|   Functionality | TX/RX Data Channel 4     |
|   Direction     | Input                    |
| AXR5            |                          |
|   Functionality | TX/RX Data Channel 5     |
|   Direction     | Input                    |
| AXR6            |                          |
|   Functionality | TX/RX Data Channel 6     |
|   Direction     | Input                    |
| AXR7            |                          |
|   Functionality | TX/RX Data Channel 7     |
|   Direction     | Input                    |
| AXR8            |                          |
|   Functionality | TX/RX Data Channel 8     |
|   Direction     | Input                    |
| AXR9            |                          |
|   Functionality | TX/RX Data Channel 9     |
|   Direction     | Input                    |
| AXR10           |                          |
|   Functionality | TX/RX Data Channel 10    |
|   Direction     | Input                    |
| AXR11           |                          |
|   Functionality | TX/RX Data Channel 11    |
|   Direction     | Input                    |
| AXR12           |                          |
|   Functionality | TX/RX Data Channel 12    |
|   Direction     | Input                    |
| AXR13           |                          |
|   Functionality | TX/RX Data Channel 13    |
|   Direction     | Input                    |
| AXR14           |                          |
|   Functionality | TX/RX Data Channel 14    |
|   Direction     | Input                    |
| AXR15           |                          |
|   Functionality | TX/RX Data Channel 15    |
|   Direction     | Input                    |
|--------------------------------------------|

#omapconf dump mcasp2

Please help us.

0 Rajee Sankar over 7 years ago in reply to Rajee Sankar

Intellectual 295 points

Any help on this please?

0 Misael Lopez Cruz over 7 years ago in reply to Rajee Sankar

TI__Genius 9325 points

Below configuration doesn't seem right:

| Receive Format Unit  |                  |
|   Slot Size          | 32 bits          |
|   Right-Rotation     | 16 bit positions |
|-----------------------------------------|

The slot size should be 16-bits and no rotation should be required.

Your current McASP settings are valid for a 64-bit frame with 2 x 32-bit slots, but the tuner is configured for a 32-bit frame with 2 x 16-bit slots. This mismatch causes below error:

|   Status            | Unexpected frame sync       |

Which means that McASP is getting the frame sync earlier than expected.

0 Rajee Sankar over 7 years ago in reply to Misael Lopez Cruz

Intellectual 295 points

Thank you Cruz!

As per your suggestion, from my application I configured 'snd_pcm_hw_params_set_format' as S16_LE instead of S32_LE. so, slot size is configured for 16bit. And I modifed rx_rotate as 0.

After this I have not observed the 'unexpected frame sync' in omapconf show mcasp2 command. But still I'm not getting the slot 1 data. Please find the register dump as below.

#./omapconf show mcasp2
ALSA Read data :-32
Read: 8192
ALSA Read data :-32
Read: 8192
ALSA Read data :-32
Read: 8192
OMAPCONF (rev 1.73-nogit built Fri Aug 30 11:12:40 IST 2019)

HW Platform:
Generic DRA74X (Flattened Device Tree)
DRA75X ES1.1 GP Device (STANDARD performance (1.5GHz))
TPS659038 ES2.0

SW Build Details:
Build:
    Version: _____                    _____           _         _
Kernel:
    Version: 3.14.63-00015-g7d1141e-dirty
    Author: jasminuser@Elakkiyapriya
    Toolchain: gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03)
    Type: #46 SMP PREEMPT
    Date: Wed Sep 4 10:14:03 IST 2019

|---------------------------------------------|
| Data Ports and Buffers                      |
|---------------------------------------------|
| Port                   | DATA bus           |
| Transmit DMA           |                    |
|   DMA request          | Enabled            |
|   Status               | No error           |
| Receive DMA            |                    |
|   DMA request          | Enabled            |
|   Status               | No error           |
| Transmit Buffer (XBUF) |                    |
|   Status               | No error           |
| Receive Buffer (RBUF) |                    |
|   Status               | No error           |
| Write FIFO (WFIFO)     |                    |
|   State                | Disabled           |
|   Threshold            | 16 samples         |
|   Level                | 0 samples in FIFO |
| Read FIFO (RFIFO)      |                    |
|   State                | Enabled            |
|   Threshold            | 32 samples         |
|   Level                | 13 samples in FIFO |
|---------------------------------------------|

|----------------------------------------|
| Control                                |
|----------------------------------------|
| Transmit State-Machine |               |
|   State                | Held in reset |
| Transmit Sequencer     |               |
|   Enabled Slots        | 2             |
|   Active Slots         | 2             |
|   Active Slots Mask    | 0x00000003    |
|   Current Slot         | Inactive      |
| Receive State-Machine |               |
|   State                | Active        |
| Receive Sequencer      |               |
|   Enabled Slots        | 2             |
|   Active Slots         | 2             |
|   Active Slots Mask    | 0x00000003    |
|   Current Slot         | 0             |
|----------------------------------------|

|-----------------------------------------------------|
| Clocks                                              |
|-----------------------------------------------------|
| Transmit Bit Clock        |                         |
|   State                   | Held in reset           |
|   Divider                 | Divide-by 1             |
|   Source                  | External (ACLKX pin)    |
|   Polarity                | Driven on rising edge   |
| Transmit High-Speed Clock |                         |
|   State                   | Held in reset           |
|   Divider                 | Divide-by 1             |
|   Source                  | Internal (AUXCLK)       |
|   Polarity                | Non-inverted            |
| Receive Bit Clock         |                         |
|   State                   | Running                 |
|   Divider                 | Divide-by 1             |
|   Source                  | External (ACLKR pin)    |
|   Polarity                | Samples on falling edge |
| Receive High-Speed Clock |                         |
|   State                   | Running                 |
|   Divider                 | Divide-by 1             |
|   Source                  | Internal (AUXCLK)       |
|   Polarity                | Non-inverted            |
| Sync Mode                 | Synchronous to TX       |
| Idle Mode                 | No-idle                 |
|-----------------------------------------------------|

|---------------------------------------------------|
| Frame Sync Generator                              |
|---------------------------------------------------|
| Transmit Frame Sync |                             |
|   Generator State   | Held in reset               |
|   Source            | External                    |
|   Polarity          | Frame starts on rising edge |
|   Pulse Width       | Single bit                  |
|   Slot Count        | 2 (TDM)                     |
|   Data Delay        | 1-bit                       |
|   Status            | No error                    |
| Receive Frame Sync |                             |
|   Generator State   | Active                      |
|   Source            | External                    |
|   Polarity          | Frame starts on rising edge |
|   Pulse Width       | Single bit                  |
|   Slot Count        | 2 (TDM)                     |
|   Data Delay        | 1-bit                       |
|   Status            | No error                    |
| Sync Mode           | Synchronous to TX           |
|---------------------------------------------------|

|-----------------------------------------|
| Format Units                            |
|-----------------------------------------|
| Transmit Format Unit |                  |
|   Slot Size          | 16 bits          |
|   Bit Mask           | 0x0000FFFF       |
|   Padding            | Pad with 0       |
|   Right-Rotation     | 16 bit positions |
|   Bitstream Order    | MSB first        |
| Receive Format Unit |                  |
|   Slot Size          | 16 bits          |
|   Bit Mask           | 0x0000FFFF       |
|   Padding            | Pad with 0       |
|   Right-Rotation     | 0 bit positions |
|   Bitstream Order    | MSB first        |
|-----------------------------------------|

|---------------------------------|
| Serializers                     |
|---------------------------------|
| Transmit Serializers | Cleared |
| Receive Serializers | Active   |
| Serializer 0         |          |
|   Mode               | Receive |
|   Inactive State     | Hi-Z     |
| Serializer 1         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 2         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 3         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 4         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 5         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 6         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 7         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 8         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 9         |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 10        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 11        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 12        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 13        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 14        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
| Serializer 15        |          |
|   Mode               | Inactive |
|   Inactive State     | Hi-Z     |
|---------------------------------|

|--------------------------------------------|
| Pin Control                                |
|--------------------------------------------|
| AFSR            |                          |
|   Functionality | Receive Frame Sync       |
|   Direction     | Input                    |
| ACLKR           |                          |
|   Functionality | Receive Bit Clock        |
|   Direction     | Input                    |
| AFSX            |                          |
|   Functionality | Transmit Frame Sync      |
|   Direction     | Input                    |
| ACLKX           |                          |
|   Functionality | Transmit Bit Clock       |
|   Direction     | Input                    |
| AHCLKX          |                          |
|   Functionality | Transmit High-Freq Clock |
|   Direction     | Input                    |
| AXR0            |                          |
|   Functionality | TX/RX Data Channel 0     |
|   Direction     | Input                    |
| AXR1            |                          |
|   Functionality | TX/RX Data Channel 1     |
|   Direction     | Input                    |
| AXR2            |                          |
|   Functionality | TX/RX Data Channel 2     |
|   Direction     | Input                    |
| AXR3            |                          |
|   Functionality | TX/RX Data Channel 3     |
|   Direction     | Input                    |
| AXR4            |                          |
|   Functionality | TX/RX Data Channel 4     |
|   Direction     | Input                    |
| AXR5            |                          |
|   Functionality | TX/RX Data Channel 5     |
|   Direction     | Input                    |
| AXR6            |                          |
|   Functionality | TX/RX Data Channel 6     |
|   Direction     | Input                    |
| AXR7            |                          |
|   Functionality | TX/RX Data Channel 7     |
|   Direction     | Input                    |
| AXR8            |                          |
|   Functionality | TX/RX Data Channel 8     |
|   Direction     | Input                    |
| AXR9            |                          |
|   Functionality | TX/RX Data Channel 9     |
|   Direction     | Input                    |
| AXR10           |                          |
|   Functionality | TX/RX Data Channel 10    |
|   Direction     | Input                    |
| AXR11           |                          |
|   Functionality | TX/RX Data Channel 11    |
|   Direction     | Input                    |
| AXR12           |                          |
|   Functionality | TX/RX Data Channel 12    |
|   Direction     | Input                    |
| AXR13           |                          |
|   Functionality | TX/RX Data Channel 13    |
|   Direction     | Input                    |
| AXR14           |                          |
|   Functionality | TX/RX Data Channel 14    |
|   Direction     | Input                    |
| AXR15           |                          |
|   Functionality | TX/RX Data Channel 15    |
|   Direction     | Input                    |
|--------------------------------------------|

# ./omapconf dump mcasp2
OMAPCONF (rev 1.73-nogit built Fri Aug 30 11:12:40 IST 2019)

HW Platform:
Generic DRA74X (Flattened Device Tree)
DRA75X ES1.1 GP Device (STANDARD performance (1.5GHz))
TPS659038 ES2.0

SW Build Details:
Build:
    Version: _____                    _____           _         _
Kernel:
    Version: 3.14.63-00015-g7d1141e-dirty
    Author: jasminuser@Elakkiyapriya
    Toolchain: gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03)
    Type: #46 SMP PREEMPT
    Date: Wed Sep 4 10:14:03 IST 2019

|--------------------------------------------|
| Reg. Name        | Reg. Addr | Reg. Val. |
|--------------------------------------------|
| MCASP_PID        | 0x48464000 | 0x44307B02 |
| PWRIDLESYSCONFIG | 0x48464004 | 0x00000001 |
| MCASP_PFUNC      | 0x48464010 | 0x00000000 |
| MCASP_PDIR       | 0x48464014 | 0x00000000 |
| MCASP_PDOUT      | 0x48464018 | 0x00000000 |
| MCASP_PDIN       | 0x4846401C | 0x48000030 |
| MCASP_PDCLR      | 0x48464020 | 0x00000000 |
| MCASP_GBLCTL     | 0x48464044 | 0x0000001F |
| MCASP_AMUTE      | 0x48464048 | 0x00000000 |
| MCASP_LBCTL      | 0x4846404C | 0x00000000 |
| MCASP_TXDITCTL   | 0x48464050 | 0x00000000 |
| MCASP_GBLCTLR    | 0x48464060 | 0x0000001F |
| MCASP_RXMASK     | 0x48464064 | 0x0000FFFF |
| MCASP_RXFMT      | 0x48464068 | 0x00018070 |
| MCASP_RXFMCTL    | 0x4846406C | 0x00000100 |
| MCASP_ACLKRCTL   | 0x48464070 | 0x00000000 |
| MCASP_AHCLKRCTL | 0x48464074 | 0x00008000 |
| MCASP_RXTDM      | 0x48464078 | 0x00000003 |
| MCASP_EVTCTLR    | 0x4846407C | 0x00000001 |
| MCASP_RXSTAT     | 0x48464080 | 0x00000154 |
| MCASP_RXTDMSLOT | 0x48464084 | 0x00000000 |
| MCASP_RXCLKCHK   | 0x48464088 | 0x14000000 |
| MCASP_REVTCTL    | 0x4846408C | 0x00000000 |
| MCASP_GBLCTLX    | 0x484640A0 | 0x0000001F |
| MCASP_TXMASK     | 0x484640A4 | 0x0000FFFF |
| MCASP_TXFMT      | 0x484640A8 | 0x00018074 |
| MCASP_TXFMCTL    | 0x484640AC | 0x00000100 |
| MCASP_ACLKXCTL   | 0x484640B0 | 0x00180000 |
| MCASP_AHCLKXCTL | 0x484640B4 | 0x00188000 |
| MCASP_TXTDM      | 0x484640B8 | 0x00000003 |
| MCASP_EVTCTLX    | 0x484640BC | 0x00000000 |
| MCASP_TXSTAT     | 0x484640C0 | 0x0000010C |
| MCASP_TXTDMSLOT | 0x484640C4 | 0x0000017F |
| MCASP_TXCLKCHK   | 0x484640C8 | 0x00000000 |
| MCASP_XEVTCTL    | 0x484640CC | 0x00000000 |
| MCASP_CLKADJEN   | 0x484640D0 | 0x00000000 |
| MCASP_XRSRCTL0   | 0x48464180 | 0x00000022 |
| MCASP_XRSRCTL1   | 0x48464184 | 0x00000000 |
| MCASP_XRSRCTL2   | 0x48464188 | 0x00000000 |
| MCASP_XRSRCTL3   | 0x4846418C | 0x00000000 |
| MCASP_XRSRCTL4   | 0x48464190 | 0x00000000 |
| MCASP_XRSRCTL5   | 0x48464194 | 0x00000000 |
| MCASP_XRSRCTL6   | 0x48464198 | 0x00000000 |
| MCASP_XRSRCTL7   | 0x4846419C | 0x00000000 |
| MCASP_XRSRCTL8   | 0x484641A0 | 0x00000000 |
| MCASP_XRSRCTL9   | 0x484641A4 | 0x00000000 |
| MCASP_XRSRCTL10 | 0x484641A8 | 0x00000000 |
| MCASP_XRSRCTL11 | 0x484641AC | 0x00000000 |
| MCASP_XRSRCTL12 | 0x484641B0 | 0x00000000 |
| MCASP_XRSRCTL13 | 0x484641B4 | 0x00000000 |
| MCASP_XRSRCTL14 | 0x484641B8 | 0x00000000 |
| MCASP_XRSRCTL15 | 0x484641BC | 0x00000000 |
| MCASP_WFIFOCTL   | 0x48465000 | 0x00001004 |
| MCASP_WFIFOSTS   | 0x48465004 | 0x00000000 |
| MCASP_RFIFOCTL   | 0x48465008 | 0x00012001 |
| MCASP_RFIFOSTS   | 0x4846500C | 0x00000011 |
|--------------------------------------------|

Please help us.

0 Misael Lopez Cruz over 7 years ago in reply to Rajee Sankar

TI__Genius 9325 points

Please check if slot-1 data is correct after changing the data delay to 0-bit. Currently, it's set to 1, but that doesn't match tuner's data format.

|   Data Delay        | 1-bit                       |

0 Misael Lopez Cruz over 7 years ago in reply to Misael Lopez Cruz

TI__Genius 9325 points

Rajee,

Is data on slot 1 correct after setting McASP data delay to 0-bit?

0 Misael Lopez Cruz over 7 years ago in reply to Misael Lopez Cruz

TI__Genius 9325 points

I haven't heard back from you, I'm assuming you were able to resolve your issue. If not, please post a reply below (or create a new thread if the thread has locked due to time-out).

Processors

Processors forum

DRA756: One slot data is missing in McASP I2S slave mode