Hi SIr
We used LPDDR2 with AM4376 for development.
Currently we used Micro LPDDR2 for development. It can boot successfully and work well.
And we changed the LPDDR2 to Nanya NT6TL256T32BQ-G0 and met some issues.
We used JTAG to connect with CPU by using below GEL setting. It can initialize well and do DDR_DataTransferCheck without error.
//********************************************************************************
// LPDDR2 Initialization
//********************************************************************************
//********************************************************************************
#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 //no pullup/down on addr/ctrl
#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 //no pullup/down on addr/ctrl
#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x00000294 //Slew rate: fast, Impedance: 44ohms, no pullup/down
#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS
#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS
#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS
#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 //Slew rate: fast, Impedance: 44ohms, pullup on DQSn, pulldown on DQS
//timings for 266MHz LPDDR2 (8Gb)
#define LPDDR2_PHY_CTRL 0x0E288007
#define LPDDR2_SDRAM_TIMING1 0xEA86B411
#define LPDDR2_SDRAM_TIMING2 0x103A0E8A
#define LPDDR2_SDRAM_TIMING3 0x5F6BA22F
//#define LPDDR2_SDRAM_CONFIG 0x808052BA //16-bit LPDDR2
#define LPDDR2_SDRAM_CONFIG 0x80801AB2//0x808012BA //32-bit LPDDR2
#define LPDDR2_REF_CTRL 0x0000040D //266 * 3.9us = 0x40d
#define LPDDR2_ZQ_CONFIG 0x5007FA67
//===========================================================================//
After integrating above setting into MLO source code, it boots failed.
We cannot find the root cause and please advise
Spec:NT6TL256T32BQ-G0.pdf
BR
Yimin
