DM36x RBL, NAND, and EM_CE

Hi,

From the DM365 DS, I cannot find any reference of the VDD_AEMIF2_18_33 can be used for a NAND boot at 1.8V.

The NAND boot mode assumes the NAND is located on the EM_CE0_ space. Please refer to the section 11.2.1 of the DM365 ARM SS (sprufg5a) for more details.

Hope this helps.

Thanks,

Tai Nguyen

Thanks, I didn't check that particular document.  So you're right, I can't boot from 1.8V NAND if AEMIF1 isn't also configured as 1.8V.  This seems like an oversight on TI's part since all other NAND signals are firmly in AEMIF2.  However for now I will just switch to a 3.3V NAND.  I was trying to avoid that because the errata discusses the 3.3V operation of configurable 1.8/3.3V banks as problematic if you don't get your signals down below 0.2V.

Thanks,

Kevin

Hi Kevin,

I agree with you. I am not sure what was the real reason behind of making only the CE0 is on power supply of VDDAEMIF1_18_33 and all other AEMIFsignals are on VDDAEMIF2_18_33. For this, you have to tie both VDDAEMIF1_18_33 and VDDAEMIF2_18_33 to the 3.3V power supply for 3.3V NAND operation.

Thanks,

Tai

I hate to re-awaken an old thread but I'd appreciate additional clarification on this subject.  First, the DM365 (and DM368) datasheet DOES state that VDD_AEMMIF2 can be at 1.8V for 8-bit NAND while VDD_AEMIF1 is at 3.3V for GPIO.  (Search for "Example 1: VDD_AEMIF2_18_33 at 1.8-V" in either datasheet).  But, as you have noted, it also says that CE0 is on VDD_AEMIF1 and CE1 is on VDD_AEMIF2 which is the reverse of what would be expected.  This is either an unfortunate mistake in the part(s) or an error in the datasheet(s).  I'm hoping for the latter.  Can you please verify?

Alternatively, to use 1.8V NAND, I can either add a level translator to EM_CE0 or use 1.8V GPIO for the affected pins.  Right?

Thanks!

Carl