Tool/software: TI C/C++ Compiler
Can someone tell the place for finding event ids and interrupt numbers for creating HWI for GPIO 8-22.
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Tool/software: TI C/C++ Compiler
Can someone tell the place for finding event ids and interrupt numbers for creating HWI for GPIO 8-22.
Hi Dhruv,
You can find GPIO interrupt numbers in AM572x TRM, section 17.3 Interrupt Controllers Integration
Check below user guide regarding HWI configuration:
Regards,
Pavel
Hi ,
please can you verify the following code for GPIO8-22 Hwi creation ?
// GPIO 8-22
#define GPIO_PORT_NUM 0x8
#define GPIO_PIN_NUM 0x16
GPIO_PinConfig gpioPinConfigs[] = {
GPIO_DEVICE_CONFIG(GPIO_FPGA_INTR_PORT_NUM, GPIO_FPGA_INTR_PIN_NUM) |
GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING
}
// Pinmux
regVal = 0x5000E;
((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VOUT1_D22 = regVal; //gpio 8_22
void intr_init() {
/* TRM : Table 17-3 DSP1_INTC Default Interrupt Mapping
* Default interrupt Mapping for GPIO8 is not there
* trying with cross-bar reserved is possible ?
*/
Hwi_Handle gpio_int_h;
Hwi_Params hwiInputParams;
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_1); // Correct ?
Hwi_Params_init(&hwiInputParams);
hwiInputParams.name = "GPIO_8_22";
hwiInputParams.arg = 0;
hwiInputParams.priority = 0;
hwiInputParams.evtId = 116; // correct ?
gpio_int_h = Hwi_create(11, (Hwi_Fxn)slot_intr_Handler, &hwiInputParams);
if (gpio_int_h == NULL)
{
Log_print0(Diags_USER1,"Error :- GPIO 8_22 Hwi not created ");
ASSERTION((0), "Error:- GPIO8_22 Hwi not created");
}
}
Thanks,
Dhruv
Dhruv,
I would suggest you to explore AM572x GPIO LED example (link below). This example is using GPIO pin and crossbar.
pdk_am57xx_1_0_15/packages//ti/drv/gpio/test/led_blink/src/am572x/GPIO_idkAM572x_board.c
pdk_am57xx_1_0_15/packages/ti/drv/gpio/test/led_blink/src/main_led_blink.c
In this example, GPIO7_22 pin is used (STATUS LED 1 Yellow).
Regards,
Pavel
Hi,
based on example, If I used GPIO2-19, I am able to get the interrupt in DSP1 but same interrupt is used in ARM linux (MPU) for other purpose. we can't use GPIO2 bank.
here we tried with gpio 2-19,
// GPIO 2-19
#define GPIO_PORT_NUM 0x2
#define GPIO_PIN_NUM 0x13
GPIO_PinConfig gpioPinConfigs[] = {
GPIO_DEVICE_CONFIG(GPIO_PORT_NUM , GPIO_PIN_NUM ) |
GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING
}
// Pinmux
regVal = 0x5000E;
((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_GPMC_CS0 = regVal;//gpio2_19
void intr_init() {
Hwi_Handle gpio_int_h;
Hwi_Params hwiInputParams;
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_56, CSL_XBAR_GPIO2_IRQ_1); // Correct ?
Hwi_Params_init(&hwiInputParams);
hwiInputParams.name = "GPIO_2_19";
hwiInputParams.arg = 0;
hwiInputParams.priority = 0;
hwiInputParams.evtId = 56; // correct ?
gpio_int_h = Hwi_create(11, (Hwi_Fxn)slot_intr_Handler, &hwiInputParams);
if (gpio_int_h == NULL)
{
Log_print0(Diags_USER1,"Error :- GPIO 2_19 Hwi not created ");
ASSERTION((0), "Error:- GPIO2_19 Hwi not created");
}
}
but when we tried with GPIO 8-22 , interrupt handler is not called. it's look-like cross-bar irq configuration is not working properly. can you help me on that ?
// Table 17-3. DSP1_INTC Default Interrupt Mapping
// CSL_XBAR_INST_DSP1_IRQ_62 : Reserved by default but can be remapped to a valid interrupt source
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_1); // Correct ?
Thanks
Dhruv
Dhruv,
Dhruv Raval said:CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_1); // Correct ?
What is the value of CTRL_CORE_DSP1_IRQ_62_63[8:0] DSP1_IRQ_62? You need to have 116 (0x74) there.
Regards,
Pavel
Hi Pavel,
// CSL_XBAR_GPIO8_IRQ_1 = 116;
#define CSL_XBAR_INST_DSP1_IRQ_62 (31U)
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_1);
DSP1 we can use crossbar value from 1-64 only. TRM : Table 17-3. DSP1_INTC Default Interrupt Mapping, find the attachment.
CSL_XBAR_INST_DSP1_IRQ_62 is reserved. we want to map GPIO8_IRQ_1 to DSP1_IRQ_62. is it possible?
Dhruv Raval said:CSL_XBAR_INST_DSP1_IRQ_62 is reserved. we want to map GPIO8_IRQ_1 to DSP1_IRQ_62. is it possible?
Yes, you can.
[8:0] DSP1_IRQ_62 default values is 31 (0x1F), which is reserved. And you can write any value from 1 to 511 (0x1FF) in this register. To map GPIO8_IRQ_1, you need to write 116 (0x74) value in this register.
Regards,
Pavel
Hi Pavel,
we tried with that but with that in DSP1 we are not able to received any interrupt. any other modification is required ?
because in TRM GPIO8 interrupt not mention in DSP1 core. any extra things we have to take care ?
ARM side GPIO bank 8 is present. it will not impact any thing correct?
******** LINUX DTB GPIO BANK 8 *********
gpio@48053000 {
compatible = "ti,omap4-gpio";
reg = <0x48053000 0x200>;
interrupts = <0x0 0x74 0x4>;
ti,hwmods = "gpio8";
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0xac>;
phandle = <0xac>;
};
gpio8_dbclk {
#clock-cells = <0x0>;
compatible = "ti,gate-clock";
clocks = <0x50>;
ti,bit-shift = <0x8>;
reg = <0x1818>;
};
******************************
Thanks,
Dhruv
Dhruv,
Dhruv Raval said:ARM side GPIO bank 8 is present. it will not impact any thing correct?
******** LINUX DTB GPIO BANK 8 *********
gpio@48053000 {
compatible = "ti,omap4-gpio";
reg = <0x48053000 0x200>;
interrupts = <0x0 0x74 0x4>;
ti,hwmods = "gpio8";
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
linux,phandle = <0xac>;
phandle = <0xac>;
};gpio8_dbclk {
#clock-cells = <0x0>;
compatible = "ti,gate-clock";
clocks = <0x50>;
ti,bit-shift = <0x8>;
reg = <0x1818>;
};******************************
I don't think this is an issue. GPIO8 is described in AM57x DTS files, but not used. GPIO2 is described in the same way and used.
GPIO8 and GPIO2 are described in below files:
linux-4.19.38/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
linux-4.19.38/arch/arm/boot/dts/dra7.dtsi
And only gpio2 is used for AM572x EVM (A15 MPU Linux):
linux-4.19.38/arch/arm/boot/dts/ti/am57xx-evm-common.dtso
linux-4.19.38/arch/arm/boot/dts/am57xx-beagle-x15-revc.dts
linux-4.19.38/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
As you stated that gpio2_19 is working fine (can generate irq towards DSP1), I would suggest you to dump and compare below register settings and make sure these are aligned:
GPIO2:
CM_L4PER_GPIO2_CLKCTRL
CTRL_CORE_PAD_GPMC_CS0
CTRL_CORE_DSP1_IRQ_56_57
GPIO_IRQSTATUS_0
GPIO_IRQSTATUS_1
GPIO_IRQSTATUS_SET_0
GPIO_IRQSTATUS_SET_1
GPIO_IRQSTATUS_CLR_0
GPIO_IRQSTATUS_CLR_1
GPIO_IRQWAKEN_0
GPIO_IRQWAKEN_1
GPIO_CTRL
GPIO_OE
GPIO_DATAIN
GPIO_DATAOUT
GPIO_DEBOUNCENABLE
GPIO_CLEARDATAOUT
GPIO_SETDATAOUT
GPIO8:
CM_L4PER_GPIO8_CLKCTRL
CTRL_CORE_PAD_VOUT1_D22
CTRL_CORE_DSP1_IRQ_62_63
GPIO_IRQSTATUS_0
GPIO_IRQSTATUS_1
GPIO_IRQSTATUS_SET_0
GPIO_IRQSTATUS_SET_1
GPIO_IRQSTATUS_CLR_0
GPIO_IRQSTATUS_CLR_1
GPIO_IRQWAKEN_0
GPIO_IRQWAKEN_1
GPIO_CTRL
GPIO_OE
GPIO_DATAIN
GPIO_DATAOUT
GPIO_DEBOUNCENABLE
GPIO_CLEARDATAOUT
GPIO_SETDATAOUT
Regards,
Pavel
Hi Pavel,
we have interrupt handler in ARM side for GPIO BANK 2. It might be possible because of that we are receiving gpio 2_19 in DSP core. we have done what you ask us to do. result is as follow.
GPIO2:
Before configure HWI and crossbar
[ 68.532] [t=0x00000009:30eff8aa] xdc.runtime.Main: GPIO read 2_19 enable interrupt
[ 68.532] [t=0x00000009:30f15d7e] xdc.runtime.Main: gpio_base_address = 0x48055000 , gpio_pin = 0x13
[ 68.532] [t=0x00000009:30f2ec49] xdc.runtime.Main: CM_L4PER_GPIO2_CLKCTRL = 0x20101
[ 68.533] [t=0x00000009:30f45bc7] xdc.runtime.Main: CTRL_CORE_PAD_GPMC_CS0 = 0x6000e
[ 68.533] [t=0x00000009:30f5b725] xdc.runtime.Main: CTRL_CORE_DSP1_IRQ_56_57 = 0xf90125
[ 68.533] [t=0x00000009:30f71ab5] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x0
[ 68.533] [t=0x00000009:30f84a5a] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 68.533] [t=0x00000009:30f9781f] xdc.runtime.Main: GPIO_IRQSTATUS_SET_0 = 0xf800001
[ 68.533] [t=0x00000009:30facda7] xdc.runtime.Main: GPIO_IRQSTATUS_SET_1 = 0x0
[ 68.533] [t=0x00000009:30fc0e50] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0xf800001
[ 68.534] [t=0x00000009:30fd7dd5] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0x0
[ 68.534] [t=0x00000009:30fec149] xdc.runtime.Main: GPIO_IRQWAKEN_0 = 0xf800001
[ 68.534] [t=0x00000009:31000300] xdc.runtime.Main: GPIO_IRQWAKEN_1 = 0x0
[ 68.534] [t=0x00000009:31012e9f] xdc.runtime.Main: GPIO_CTRL = 0x2
[ 68.534] [t=0x00000009:31024311] xdc.runtime.Main: GPIO_OE = 0xffffffe1
[ 68.534] [t=0x00000009:31036f38] xdc.runtime.Main: GPIO_DATAIN = 0x1fffdf1e
[ 68.534] [t=0x00000009:3104a8dc] xdc.runtime.Main: GPIO_DATAOUT = 0x1e
[ 68.535] [t=0x00000009:3105e2f8] xdc.runtime.Main: GPIO_DEBOUNCENABLE = 0xf800001
[ 68.535] [t=0x00000009:31073634] xdc.runtime.Main: GPIO_CLEARDATAOUT = 0x1e
[ 68.535] [t=0x00000009:31087095] xdc.runtime.Main: GPIO_SETDATAOUT = 0x1e
After receiving interrupt configure HWI and crossbar
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_56, CSL_XBAR_GPIO2_IRQ_1);
[ 73.100] [t=0x00000009:cdc67b90] xdc.runtime.Main: GPIO read 2_19 enable interrupt
[ 73.100] [t=0x00000009:cdc7d49f] xdc.runtime.Main: gpio_base_address = 0x48055000 , gpio_pin = 0x13
[ 73.101] [t=0x00000009:cdc96e93] xdc.runtime.Main: CM_L4PER_GPIO2_CLKCTRL = 0x20101
[ 73.101] [t=0x00000009:cdcac60a] xdc.runtime.Main: CTRL_CORE_PAD_GPMC_CS0 = 0x6000e
[ 73.101] [t=0x00000009:cdcc1ccc] xdc.runtime.Main: CTRL_CORE_DSP1_IRQ_56_57 = 0xf80019
[ 73.101] [t=0x00000009:cdcd8049] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x0
[ 73.101] [t=0x00000009:cdceb668] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 73.101] [t=0x00000009:cdcfe928] xdc.runtime.Main: GPIO_IRQSTATUS_SET_0 = 0xf800001
[ 73.102] [t=0x0000
[ 73.102] [t=0x00000009:cdd14d82] xdc.runtime.Main: GPIO_IRQSTATUS_SET_1 = 0x0
[ 73.102] [t=0x00000009:cdd2ae4d] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0xf800001
[ 73.102] [t=0x00000009:cdd54716] xdc.runtime.Main: GPIO_IRQWAKEN_0 = 0xf800001
[ 73.102] [t=0x00000009:cdd68c66] xdc.runtime.Main: GPIO_IRQWAKEN_1 = 0x0
[ 73.102] [t=0x00000009:cdd7ba03] xdc.runtime.Main: GPIO_CTRL = 0x2
[ 73.102] [t=0x00000009:cdd8d2cc] xdc.runtime.Main: GPIO_OE = 0xffffffe1
[ 73.103] [t=0x00000009:cdda0c12] xdc.runtime.Main: GPIO_DATAIN = 0x1fffdf1e
[ 73.103] [t=0x00000009:cddb47ad] xdc.runtime.Main: GPIO_DATAOUT = 0x1e
[ 73.103] [t=0x00000009:cddc6ce9] xdc.runtime.Main: GPIO_DEBOUNCENABLE = 0xf800001
[ 73.103] [t=0x00000009:cdddbc0d] xdc.runtime.Main: GPIO_CLEARDATAOUT = 0x1e
[ 73.103] [t=0x00000009:cddef80a] xdc.runtime.Main: GPIO_SETDATAOUT = 0x1e
GPIO8:
Before configure HWI and crossbar
[ 107.439] [t=0x0000000e:68bc4855] xdc.runtime.Main: gpio_base_address = 0x48053000 , gpio_pin = 0x16
[ 107.440] [t=0x0000000e:68be07c3] xdc.runtime.Main: CM_L4PER_GPIO8_CLKCTRL = 0x20001
[ 107.440] [t=0x0000000e:68bf6960] xdc.runtime.Main: CTRL_CORE_PAD_VOUT1_D22 = 0x6000e
[ 107.440] [t=0x0000000e:68c0cbf5] xdc.runtime.Main: CTRL_CORE_DSP1_IRQ_62_63 = 0x20001f
[ 107.440] [t=0x0000000e:68c235b0] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x0
[ 107.440] [t=0x0000000e:68c36c15] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 107.440] [t=0x0000000e:68c4a246] xdc.runtime.Main: GPIO_IRQSTATUS_SET_0 = 0x0
[ 107.441] [t=0x0000000e:68c5fe3d] xdc.runtime.Main: GPIO_IRQSTATUS_SET_1 = 0x0
[ 107.441] [t=0x0000000e:68c746ac] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0x0
[ 107.441] [t=0x0000000e:68c88d91] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0x0
[ 107.441] [t=0x0000000e:68c9d542] xdc.runtime.Main: GPIO_IRQWAKEN_0 = 0x0
[ 107.441] [t=0x0000000e:68cb0751] xdc.runtime.Main: GPIO_IRQWAKEN_1 = 0x0
[ 107.441] [t=0x0000000e:68cc39a7] xdc.runtime.Main: GPIO_CTRL = 0x2
[ 107.441] [t=0x0000000e:68cd55e4] xdc.runtime.Main: GPIO_OE = 0xfff4eebf
[ 107.442] [t=0x0000000e:68cea176] xdc.runtime.Main: GPIO_DATAIN = 0xd8d711da
[ 107.442] [t=0x0000000e:68cfe56d] xdc.runtime.Main: GPIO_DATAOUT = 0xb1140
[ 107.442] [t=0x0000000e:68d11edb] xdc.runtime.Main: GPIO_DEBOUNCENABLE = 0x0
[ 107.442] [t=0x0000000e:68d25e2b] xdc.runtime.Main: GPIO_CLEARDATAOUT = 0xb1140
[ 107.442] [t=0x0000000e:68d3a858] xdc.runtime.Main: GPIO_SETDATAOUT = 0xb1140
After receiving interrupt configure HWI and crossbar
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_1);
[ 162.046] [t=0x00000015:bb7f5e97] xdc.runtime.Main: GPIO read 8_22 enable interrupt
[ 162.046] [t=0x00000015:bb80bcc8] xdc.runtime.Main: gpio_base_address = 0x48053000 , gpio_pin = 0x16
[ 162.046] [t=0x00000015:bb8259a9] xdc.runtime.Main: CM_L4PER_GPIO8_CLKCTRL = 0x20001
[ 162.046] [t=0x00000015:bb83b853] xdc.runtime.Main: CTRL_CORE_PAD_VOUT1_D22 = 0x6000e
[ 162.047] [t=0x00000015:bb853d7b] xdc.runtime.Main: CTRL_CORE_DSP1_IRQ_62_63 = 0x200074
[ 162.047] [t=0x00000015:bb86a9fc] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x0
[ 162.047] [t=0x00000015:bb87e0ac] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 162.047] [t=0x00000015:bb89169f] xdc.runtime.Main: GPIO_IRQSTATUS_SET_0 = 0x0
[ 162.047] [t=0x00000015:bb8a5e26] xdc.runtime.Main: GPIO_IRQSTATUS_SET_1 = 0x0
[ 162.047] [t=0x00000015:bb8ba325] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0x0
[ 162.047] [t=0x00000015:bb8cea94] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0x0
[ 162.048] [t=0x00000015:bb8e4a26] xdc.runtime.Main: GPIO_IRQWAKEN_0 = 0x0
[ 162.048] [t=0x00000015:bb8f7e2e] xdc.runtime.Main: GPIO_IRQWAKEN_1 = 0x0
[ 162.048] [t=0x00000015:bb90b25e] xdc.runtime.Main: GPIO_CTRL = 0x2
[ 162.048] [t=0x00000015:bb9231c8] xdc.runtime.Main: GPIO_OE = 0xfff4eebf
[ 162.048] [t=0x00000015:bb9369ef] xdc.runtime.Main: GPIO_DATAIN = 0xd8d711ca
[ 162.048] [t=0x00000015:bb94ab46] xdc.runtime.Main: GPIO_DATAOUT = 0xb1140
[ 162.048] [t=0x00000015:bb95e5a1] xdc.runtime.Main: GPIO_DEBOUNCENABLE = 0x0
[ 162.049] [t=0x00000015:bb973b65] xdc.runtime.Main: GPIO_CLEARDATAOUT = 0xb1140
[ 162.049] [t=0x00000015:bb9887b7] xdc.runtime.Main: GPIO_SETDATAOUT = 0xb1140
ac] xdc.runtime.Main: GPIO_IRQSTATUS_CLR_0 = 0x0
we are using rpmsg (remote proc) to bootstrap the DSP1 core, It's look like we have to some more configuration for enable HWI for GPIO8 in DSP1 core. please let us know if any extra configuration is require? how to do it ?
Thanks,
Dhruv
Dhruv,
From what I understand, you are receiving external interrupt signal on AM572x GPIO pins. I would suggest you also to probe with scope these pins, gpio2_19 T1 and gpio8_22 B9 and verify you are receiving valid interrupt signals on these pins from external source.
Also I see in register GPIO2.GPIO_IRQSTATUS_SET_0 (which is valid for GPIO2_IRQ_1) you have 0xf800001, which means gpio2_19 interrupt is disabled, while gpio2_0 and gpio2_[27:23] are enabled. So your GPIO2_IRQ_1 irq in DSP1 might be coming NOT from gpio2_19, but from other gpio2 pins. You can check this.
In register GPIO8.GPIO_IRQSTATUS_SET_0 you have 0x0, which means that gpio8_22 and all other gpio8 pins interrupt generation is disabled. You need to enable gpio8_22 event in this register, GPIO8.GPIO_IRQSTATUS_SET_0[22] INTLINE should be 1 for GPIO8_IRQ_1
Regards,
Pavel
Hi Pavel,
What you observed is correct for gpio bank 2, in ARM linux side we have written interrupt handler, because of that in DSP core also we are receiving interrupt,
we don't know why both ARM and DSP getting interrupt.
For GPIO Bank 8, gpio 8_22 is connected to FPGA, FPGA is giving every 9th milliseconds interrupt to DSP.
if we use GPIO8 interrupt 1 than ARM linux following error occurring after receiving 1st interrupt in DSP core.
************************************************ configure gpio 8_22 hwi interrupt GPIO8_IRQ_1 DSP **********************************
uint32_t gpio_base_address = SOC_GPIO8_BASE; //0x48053000U
uint32_t gpio_pin = 0x16; //22
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_1);
GPIO_init();
GPIOModuleReset(gpio_base_address);
GPIOModuleEnable(gpio_base_address);
GPIOIntTypeSet(gpio_base_address, gpio_pin, GPIO_INT_TYPE_RISE_EDGE);
GPIODirModeSet(gpio_base_address, gpio_pin, GPIO_DIR_INPUT);
GPIOPinIntDisable(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
GPIOPinIntClear(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
GPIOTriggerPinInt(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
GPIOPinIntEnable(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
GPIOPinIntWakeUpEnable(gpio_base_address,GPIO_INT_LINE_1,gpio_pin);
Hwi_Handle gpio_int_h;
Hwi_Params hwiInputParams;
Hwi_Params_init(&hwiInputParams);
hwiInputParams.name = "GPIO_8_22";
hwiInputParams.arg = 0;
hwiInputParams.priority = 0;
hwiInputParams.evtId = 62
gpio_int_h = Hwi_create(11, (Hwi_Fxn)slot_intr_Handler, &hwiInputParams);
if (gpio_int_h == NULL)
{
Log_print0(Diags_USER1,"Error :- GPIO 8_22 Hwi not created ");
ASSERTION((0), "Error:- GPIO8_22 Hwi not created");
}
}
**************************************************************************************************************************
************************************* ARM Linux Error ****************************************************************
root@am57xx-phycore-rdk:~# [ 102.046857] irq 289, desc: eea50000, depth: 1, count: 0, unhandled: 0
[ 102.053334] ->handle_irq(): c007e908, handle_bad_irq+0x0/0x280
[ 102.059296] ->irq_data.chip(): eea4ed90, 0xeea4ed90
[ 102.064203] ->action(): (null)
[ 102.067442] IRQ_NOPROBE set
[ 102.070506] unexpected IRQ trap at vector 121
*****************************************************************************************************
if we use GPIO8 interrupt q than ARM linux error not happen with GPIOPinIntDisable(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);. but we are receiving so unwanted interrupt in DSP core every 300 micro-seconds. we can use only gpio 8 interrupt 2, correct? because gpio 8 interrupt 1 is mapped to MPU (ARM linux)
************************************************ configure gpio 8_22 hwi interrupt GPIO8_IRQ_2 DSP **********************************
uint32_t gpio_base_address = SOC_GPIO8_BASE; //0x48053000U
uint32_t gpio_pin = 0x16; //22
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_2);
GPIO_init();
GPIOModuleReset(gpio_base_address);
GPIOModuleEnable(gpio_base_address);
GPIOIntTypeSet(gpio_base_address, gpio_pin, GPIO_INT_TYPE_RISE_EDGE);
GPIODirModeSet(gpio_base_address, gpio_pin, GPIO_DIR_INPUT);
GPIOPinIntDisable(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
GPIOPinIntClear(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
GPIOTriggerPinInt(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
GPIOPinIntEnable(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
GPIOPinIntWakeUpEnable(gpio_base_address,GPIO_INT_LINE_2,gpio_pin);
GPIOPinIntDisable(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
GPIOPinIntClear(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
Hwi_Handle gpio_int_h;
Hwi_Params hwiInputParams;
Hwi_Params_init(&hwiInputParams);
hwiInputParams.name = "GPIO_8_22";
hwiInputParams.arg = 0;
hwiInputParams.priority = 0;
hwiInputParams.evtId = 62
gpio_int_h = Hwi_create(11, (Hwi_Fxn)slot_intr_Handler, &hwiInputParams);
if (gpio_int_h == NULL)
{
Log_print0(Diags_USER1,"Error :- GPIO 8_22 Hwi not created ");
ASSERTION((0), "Error:- GPIO8_22 Hwi not created");
}
}
void slot_intr_Handler (UINT32 * arg)
{
static int count = 0,i=0;
GPIOPinIntDisable(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
//GPIO_PROFILING : gpio 8_13
GPIO_write(GPIO_PROFILING, GPIO_PIN_VAL_HIGH);
for(i=0;i<1000;i++);
GPIO_write(GPIO_PROFILING, GPIO_PIN_VAL_LOW);
Log_print1(Diags_USER1, "***** fpga_gpio_interrupt_Handler count = %d ***** ",count++);
}
**************************************************************************************************************************
here is dump values for GPIO8 bank:
******************** Before Hwi configuration ***************
GPIO read 8_22 enable interrupt
gpio_base_address = 0x48053000 , gpio_pin = 0x16
CM_L4PER_GPIO8_CLKCTRL = 0x20101
CTRL_CORE_PAD_VOUT1_D22 = 0x5000e
CTRL_CORE_DSP1_IRQ_62_63 = 0x20001f
GPIO_IRQSTATUS_1 = 0x0
GPIO_IRQSTATUS_0 = 0x0
GPIO_IRQSTATUS_SET_0 = 0x0
GPIO_IRQSTATUS_SET_1 = 0x0
GPIO_IRQSTATUS_CLR_0 = 0x0
GPIO_IRQSTATUS_CLR_1 = 0x0
GPIO_IRQWAKEN_0 = 0x0
GPIO_IRQWAKEN_1 = 0x0
GPIO_CTRL = 0x2
GPIO_OE = 0xfff4cebf
GPIO_DATAIN = 0xd81711ca
GPIO_DATAOUT = 0xb1140
GPIO_DEBOUNCENABLE = 0x0
GPIO_CLEARDATAOUT = 0xb1140
GPIO_SETDATAOUT = 0xb1140
GPIO read 8_13 enable interrupt
CM_L4PER_GPIO8_CLKCTRL = 0x20101
CTRL_CORE_PAD_VOUT1_D13 = 0x7000e
GPIO_IRQSTATUS_1 = 0x0
GPIO_IRQSTATUS_0 = 0x0
GPIO_IRQSTATUS_SET_0 = 0x0
GPIO_IRQSTATUS_SET_1 = 0x0
GPIO_IRQSTATUS_CLR_0 = 0x0
GPIO_IRQSTATUS_CLR_0 = 0x0
GPIO_IRQWAKEN_0 = 0x0
GPIO_IRQWAKEN_1 = 0x0
GPIO_CTRL = 0x2
GPIO_OE = 0xfff4cebf
GPIO_DATAIN = 0xd81711da
GPIO_DATAOUT = 0xb1140
GPIO_DEBOUNCENABLE = 0x0
GPIO_CLEARDATAOUT = 0xb1140
GPIO_SETDATAOUT = 0xb1140
************************* END ***************************
******************** After Hwi configuration *************
GPIO read 8_22 enable interrupt
gpio_base_address = 0x48053000 , gpio_pin = 0xd
CM_L4PER_GPIO8_CLKCTRL = 0x20101
CTRL_CORE_PAD_VOUT1_D22 = 0x5000e
CTRL_CORE_DSP1_IRQ_62_63 = 0x20015c
GPIO_IRQSTATUS_1 = 0x400000
GPIO_IRQSTATUS_0 = 0x0
GPIO_IRQSTATUS_SET_0 = 0x0
GPIO_IRQSTATUS_SET_1 = 0x400000
GPIO_IRQSTATUS_CLR_0 = 0x0
GPIO_IRQSTATUS_CLR_1 = 0x400000
GPIO_IRQWAKEN_0 = 0x0
GPIO_IRQWAKEN_1 = 0x400000
GPIO_CTRL = 0x2
GPIO_OE = 0x400000
GPIO_DATAIN = 0xd847114a
GPIO_DATAOUT = 0xb1140
GPIO_DEBOUNCENABLE = 0x0
GPIO_CLEARDATAOUT = 0xb1140
GPIO_SETDATAOUT = 0xb1140
GPIO read 8_13 enable interrupt
CM_L4PER_GPIO8_CLKCTRL = 0x20101
CTRL_CORE_PAD_VOUT1_D13 = 0x7000e
GPIO_IRQSTATUS_1 = 0x400000
GPIO_IRQSTATUS_0 = 0x0
GPIO_IRQSTATUS_SET_0 = 0x0
GPIO_IRQSTATUS_SET_1 = 0x400000
GPIO_IRQSTATUS_CLR_0 = 0x0
GPIO_IRQSTATUS_CLR_0 = 0x400000
GPIO_IRQWAKEN_0 = 0x0
GPIO_IRQWAKEN_1 = 0x400000
GPIO_CTRL = 0x2
GPIO_OE = 0x400000
GPIO_DATAIN = 0xd847114a
GPIO_DATAOUT = 0xb1140
GPIO_DEBOUNCENABLE = 0x0
GPIO_CLEARDATAOUT = 0xb1140
GPIO_SETDATAOUT = 0xb1140
************************* END ***************************
Now gpio interrupt configuration is only enable for gpio 8_22, why we receiving so many interrupts, basically we should receive interrupt every 9th milliseconds only.
please look at the logs,
Please find the attached image. Green probe : FPGA 8-22 interrupt , yellow probe: GPIO_PROFILE 8_13 when we received interrupt.
Thanks,
Dhruv
Hi Pavel,
Now we are not getting so many interrupts, but we are getting sometime 2 interrupt call within 9th millisecond, and also gpio interrupt latency sometime is more than 1 millisecond.
here is our change,
************************************************ configure gpio 8_22 hwi interrupt GPIO8_IRQ_2 DSP **********************************
uint32_t gpio_base_address = SOC_GPIO8_BASE; //0x48053000U
uint32_t gpio_pin = 0x16; //22
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_62, CSL_XBAR_GPIO8_IRQ_2);
GPIO_init();
GPIOModuleReset(gpio_base_address);
GPIOModuleEnable(gpio_base_address);
GPIOIntTypeSet(gpio_base_address, gpio_pin, GPIO_INT_TYPE_RISE_EDGE);
GPIODirModeSet(gpio_base_address, gpio_pin, GPIO_DIR_INPUT);
GPIOPinIntDisable(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
GPIOPinIntClear(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
GPIOPinIntEnable(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
Hwi_Handle gpio_int_h;
Hwi_Params hwiInputParams;
Hwi_Params_init(&hwiInputParams);
hwiInputParams.name = "GPIO_8_22";
hwiInputParams.arg = 0;
hwiInputParams.priority = 0;
hwiInputParams.evtId = 62
gpio_int_h = Hwi_create(11, (Hwi_Fxn)slot_intr_Handler, &hwiInputParams);
if (gpio_int_h == NULL)
{
Log_print0(Diags_USER1,"Error :- GPIO 8_22 Hwi not created ");
ASSERTION((0), "Error:- GPIO8_22 Hwi not created");
}
}
void slot_intr_Handler (UINT32 * arg)
{
static int count = 0,i=0;
GPIOPinIntClear(gpio_base_address, GPIO_INT_LINE_2, gpio_pin);
//GPIO_PROFILING : gpio 8_13
GPIO_write(GPIO_PROFILING, GPIO_PIN_VAL_HIGH);
for(i=0;i<1000;i++);
GPIO_write(GPIO_PROFILING, GPIO_PIN_VAL_LOW);
Log_print1(Diags_USER1, "***** fpga_gpio_interrupt_Handler count = %d ***** ",count++);
}
1. Why our interrupt handler called by 2 times?
2. why so much latency we observed some time?
Thanks,
Dhruv
1.
2. GPIO interrupt latency some time more than 1 millisecond.
3. GPIO interrupt handler called 2 times.
Hi Pavel,
we got some more observation, actually we have registered 2 Hwi, one for PCI interface and one for GPIO 8-22, PCI interrupt handler was already present in project code base, but PIC Hwi has different EventId and Interrupt number,
***************************************** PCIE Hwi Configuration *****************************************
HwiP_Params hwiInputParams;
uint32_t cpuEvent = 48;
uint32_t xbarIndex = cpuEvent - 31;
uint32_t vector = 12;
CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_DSP1, xbarIndex, CSL_XBAR_PCIe_SS1_IRQ_INT1);
HwiP_Params_init (&hwiInputParams);
hwiInputParams.name = "PCIEEP_MSI_AND_INTX";
hwiInputParams.arg = (uintptr_t)ephandle;
hwiInputParams.priority = 0;
hwiInputParams.evtId = cpuEvent;
ephandle->pcieHwi = HwiP_create(vector, PCIE_EP_Isr, &hwiInputParams);
if (! ephandle->pcieHwi)
{
PCIE_logPrintf("Hwi create failed\n");
}
Its possible that both interrupt came as same time, how we can handle that ? we are not sure but it's look like when both interrupt came as same time we are getting 2 time interrupt handler called.
Thanks,
Dhruv
yello probe : GPIO8_22 interrupt handler gpio probe
green probe : PCIE interrupt handler gpio probe
1. Interrupt handler called once.
2. interrupt handler called 2 times.
3.
Dhruv,
I am not sure I understand your latest question.
Do you have gpio8_22 irq towards DSP1 core working now?
And your gpio8_22 interrupt handler (ISR) is called by both gpio8_22 irq event and PCIe event? And you need this handler to be called only by gpio8_22 irq event?
Regards,
Pavel
Hi Pavel,
we are using pdk_am57xx_1_0_7.
Do you have gpio8_22 irq towards DSP1 core working now?
It's not working properly, gpio 8_22 ISR called 2 times, for receiving single interrupt from FPGA.
your gpio8_22 interrupt handler (ISR) is called by both gpio8_22 irq event and PCIe event? And you need this handler to be called only by gpio8_22 irq event?
Yes, PCI interrupt handler has different ISR function, gpio8_22 interrupt handler also have different event-id and interrupt number,
GPIO8_22 interrupt handler, it shoyld call only one time, why it's called 2 times?
please help me on that.
Thanks
Dhruv.
Dhruv,
gpio 8_22 ISR called 2 times, 2 times from GPIO8 module?
Or gpio 8_22 ISR called 2 times, 1 time from GPIO8 module and 1 time from PCIe module?
Note that you need to configure your interrupt with CSL_xbarIrqConfigure() or statically with cfg script, but NOT both at the same time.
I would suggest you to explore AM572x GPIO LED example (link below). This example is using GPIO pin and crossbar.
pdk_am57xx_1_0_15/packages//ti/drv/gpio/test/led_blink/src/am572x/GPIO_idkAM572x_board.c
pdk_am57xx_1_0_15/packages/ti/drv/gpio/test/led_blink/src/main_led_blink.c
pdk_am57xx_1_0_15/packages/ti/drv/gpio/test/led_blink/am572x/c66/bios/gpio_test_idkAM572x.cfg
Regards,
Pavel
Hi Pavel,
Thanks for the reply,
gpio 8_22 ISR called 2 times, 2 times from GPIO8 module?
Yes, It's look like from GPIO8 module only, we are doing configuration with CSL_xbarIrqConfigure(); only, we are not configuring statically with cfg script.
we tried with GPIO led example code, we are not getting any interrupt in DSP and Linux console continues IRQ error showing,
here is code example,
#define GPIO_FPGA_INTR_PORT_NUM 0x8
#define GPIO_FPGA_INTR_PIN_NUM 0x16
enum BOSE_GPIO_CONFIG_INDEX {
GPIO_FPGA_INTR,
};
GPIO_PinConfig gpioPinConfigs[] = {
GPIO_DEVICE_CONFIG(GPIO_FPGA_INTR_PORT_NUM, GPIO_FPGA_INTR_PIN_NUM) |
GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING,
}
GPIO_v1_Config GPIO_v1_config = {
gpioPinConfigs,
gpioCallbackFunctions,
sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
0x20,
};
GPIO_CallbackFxn gpioCallbackFunctions[] = {NULL};
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1,CSL_XBAR_INST_DSP1_IRQ_62,CSL_XBAR_GPIO8_IRQ_1);
GPIO_setCallback(GPIO_FPGA_INTR, slot_intr_Handler);
GPIO_enableInt(GPIO_FPGA_INTR);
tried with :- CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1,CSL_XBAR_INST_DSP1_IRQ_62,CSL_XBAR_GPIO8_IRQ_2); also, same observation.
Note: GPIO BANK8 interrupts by default not mapped with DSP1 core.
Thanks,
Dhruv
Hi Pavel,
one more observation we got,
GPIO4_20 is also interrupt line from FPGA to AM572x, from linux side already that interrupt handler present, but when we tried in DSP the same interrupt,
DSP interrupt is missing, might be because linux side also same interrupt handler present.
****************************************************************************
#define GPIO_FPGA_INTR_PORT_NUM 0x4
#define GPIO_FPGA_INTR_PIN_NUM 0x14
GPIO_setCallback(GPIO_FPGA_INTR, slot_intr_Handler);
GPIO_enableInt(GPIO_FPGA_INTR);
// no need for corssbar
****************************************************************************
Thanks,
Dhruv
Dhruv Raval said:gpio 8_22 ISR called 2 times, 2 times from GPIO8 module?
Yes, It's look like from GPIO8 module only, we are doing configuration with CSL_xbarIrqConfigure(); only, we are not configuring statically with cfg script.
Dhruv,
Can you attach your main C file?
When you receive the first interrupt, do you clear it in GPIO_IRQSTATUS register? Is it possible to receive second signal on that gpio line, which is triggering the second interrupt?
Can you also put breakpoint at the beginning of your GPIO ISR and dump the GPIO registers?
Regards,
Pavel
Hi Pavel,
We don't have stand-alone project for test. We tried to disable PCIE Driver , after disabling the driver we are not receiving 2 times interrupt. ISR handler also called 1 time. but ISR latency is too much, after disable PCIE driver, around max = 5.33 ms min = 400 us. we didn't have any clue why PCIE driver have conflict with GPIO8_22 ISR.
we have result with disabling PCIE driver,
/********************************************************************* Logs Start *********************************************************************************************/
[ 53.811] [t=0x00000007:37832411] xdc.runtime.Main: ******************** Before clear ISR STATUS ***********************
[ 53.811] [t=0x00000007:3784956f] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 53.811] [t=0x00000007:378582b2] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x400000
[ 53.811] [t=0x00000007:378679f7] xdc.runtime.Main: ******************** After clear ISR STATUS ***********************
[ 53.811] [t=0x00000007:3787ced6] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 53.811] [t=0x00000007:3788bc2a] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x0
[ 53.811] [t=0x00000007:3789a6f7] xdc.runtime.Main: ******************** END ***********************
[ 53.812] [t=0x00000007:378b2a93] xdc.runtime.Main: ***** fpga_gpio_interrupt_Handler TIME = 9560 micro sec arg = 50 *****
[ 53.812] [t=0x00000007:378c9488] xdc.runtime.Main: ******************** Before clear ISR STATUS ***********************
[ 53.812] [t=0x00000007:378dece5] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 53.812] [t=0x00000007:378ed9ee] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x0
[ 53.812] [t=0x00000007:378fc4d3] xdc.runtime.Main: ******************** After clear ISR STATUS ***********************
[ 53.812] [t=0x00000007:379117b0] xdc.runtime.Main: GPIO_IRQSTATUS_0 = 0x0
[ 53.812] [t=0x00000007:379204e4] xdc.runtime.Main: GPIO_IRQSTATUS_1 = 0x0
[ 53.812] [t=0x00000007:3792efab] xdc.runtime.Main: ******************** END ***********************
[ 53.813] [t=0x00000007:379471d3] xdc.runtime.Main: ***** fpga_gpio_interrupt_Handler TIME = 1018 micro sec arg = 50 *****
/********************************************************************* Logs End *********************************************************************************************/
It's look-like when 2 time ISR handler called GPIO_IRQSTATUS_1 is already cleared.
Thanks,
Dhruv
Dhruv,
I can provide you below suggestions:
1. Make sure you are not using gpio8_22 on Linux side also. Check below e2e threads for details:
2. By default PCIe interrupts are mapped to DSP1_IRQ_48/38/39 in below files:
pdk_am57xx_1_0_15/packages/ti/csl/example/pcie/write_loopback/rc/rc_write_loopback_app_main.c
pdk_am57xx_1_0_15/packages/ti/csl/example/pcie/write_loopback/ep/ep_write_loopback_app_main.c
pdk_am57xx_1_0_15/packages/ti/drv/pcie/example/sample/am57x/src/pcie_sample_board.c
Make sure you are not changing PCIe driver to map PCIe irq to DSP1_IRQ_62
3. You ISR slot_intr_Handler() looks very huge, but it should be as small/fast as possible. Please align it to main_led_blink.c ISR AppGpioCallbackFxn().
Regards,
Pavel
Hi Pavel ,
1. Make sure you are not using gpio8_22 on Linux side also. Check below e2e threads for details:
- > we check in linux side, no one is using GPIO8_22.
2. By default PCIe interrupts are mapped to DSP1_IRQ_48/38/39 in below files:
-> we didn't change anything in PCIE driver
3. You ISR slot_intr_Handler() looks very huge, but it should be as small/fast as possible. Please align it to main_led_blink.c ISR AppGpioCallbackFxn().
-> we changed the ISR function, we are only doing sempost from there, but still that 2 interrupt issue observed.
Thanks
Dhruv
Dhruv Raval said:2. By default PCIe interrupts are mapped to DSP1_IRQ_48/38/39 in below files:
-> we didn't change anything in PCIE driver
And do you make any changes for PCIe in your custom application?
Dhruv Raval said:3. You ISR slot_intr_Handler() looks very huge, but it should be as small/fast as possible. Please align it to main_led_blink.c ISR AppGpioCallbackFxn().
-> we changed the ISR function, we are only doing sempost from there, but still that 2 interrupt issue observed.
Two interrupts from GPIO8 module? Or 1 interrupt from GPIO8 and 1 interrupt from PCIe? What is the latest status? If 1 from PCIe, how do you define you have PCIe interrupt captured in your GPIO ISR?
Can you please share the latest versions of your GPIO_setCallback(), GPIO_enableInt() and slot_intr_Handler() functions? What value you have in GPIO_IRQSTATUS_SET register?
Regards,
Pavel