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CCS/AM3359: GPMC timing configuration

Tam Nguyen2
Prodigy 140 points
Part Number: AM3359

Tool/software: Code Composer Studio

My plan is using ICEV22AM3359 with RTOS SDK 5.01.00.11.

Its communicate with NORLike external memory by GPMC connector.

Using CS2 with 16 bit, Asyn Write/Read configuration. But My problemis timing settings.

 Im using sample timing param likes it:

0U, /* csOnTime */
30U, /* csRdOffTime */
30U, /* csWrOffTime */
1U, /* advOnTime */
3U, /* advRdOffTime */
3U, /* advWrOffTime */
0U, /* advAadMuxOnTime */
0U, /* advAadMuxRdOffTime */
0U, /* advAadMuxWrOffTime */
13U, /* weOnTime */
28U, /* weOffTime */
5U, /* oeOnTime */
28U, /* oeOffTime */
0U, /* oeAadMuxOnTime */
0U, /* oeAadMuxOffTime */
0U, /* pageBurstAccessTime */
24U, /* rdAccessTime */
13U, /* wrAccessTime */
31U, /* rdCycleTime */
31U, /* wrCycleTime */
7U, /* wrDataOnMuxBusTime */
5U, /* cycle2CycleDelay */
GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY, /* cycleDelaySameChipSel */
GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY, /* cycleDelayDiffChipSel */
0U /* busTurnAroundTime */
},

My question is: Have any suggestion for timing configuration with External Read/Write timing (MKY of Step Technica)

This is GPMC timing of MKY:

  • 0
    TI__Mastermind 30110 points

    Hi Tam,

    The parameters to the GPMC like those you have shared dictate the timing of the signals. They are measured in GPMC_FCLK cycles.

    The GPMC_FCLK on AM335x should be running at 100Mhz, so each GPMC_FCLK cycle is 10ns.

    For example when advOnTime is set to 1, it means that 10ns after the start of the GPMC access the ADVn signal will assert low. Since advRdOffTime and advWrOffTime are both set to 3, for reads and writes ADVn will deassert high after 3 GPMC_FCLK cycles or 30ns after the start of the access.

    The address becomes valid at the beginning of the access cycle, so you can start with the delay requirement from address to CSn going low to determine the csOnTime, and then work your way from left to right until the csOffTime.

    For more granularity, there are ways to assert/deassert a signal half way between one GPMC_FCLK cycle by using the extradelay feature (csExtraDelay, OEExtraDelay, etc.)

    The TRM has a section on GPMC with some explanations of the different modes like synchronous and asynchronous. Non-muxed and muxed (where the address is transferred over the AD-bus (data).

    It is easiest if you can observe the signals on an oscilloscope or logic analyzer as you become familiar with the parameters.

    Let me know if you become stuck, and I'll help out as needed.

    Hope this helps,
    Mark

  • 0 in reply to Mark M
    Prodigy 140 points

    Thanks for your help.

    Look at this picture. I have read the TRM, this error looks like address not supported. But address is GPMC register region, and I dont know what does it mean.