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TDA2SA: tda2xx SD card can not boot in SD Boot mode

Part Number: TDA2SA

Hi,

My custom board can't boot up in SD boot mode.

I have tested the SD card can boot on tda2xx RVP board when setting the SD boot mode.

I don't know if the hardware is good so I load the sd boot image

VSDK_03_07\vision_sdk\binaries\apps\tda2xx_rvp_bios_all\sbl\sd\opp_nom\tda2xx-rvp\sbl_sd_opp_nom_a15_0_debug.xa15fg

It will open the AppImage file in SD card.

When debug in CCS, the log below.

 TDA2xx SBL Boot

 DPLL Configuration Completed

 Clock Domain Configuration Completed

 Module Enable Configuration Completed

 TI EVM PAD Config Completed
ERROR: HW-Leveling time-out

 DDR Config Completed

 App Image Download Begins

(it stop here)

----------------------------------------------------------------

I found when execute MMCSDCardInit() step , it get stuck in 

HSMMCSDXferStatusGet()  while loop.

hsmmcsd_API.c:

static uint32_t HSMMCSDXferStatusGet(mmcsdCtrlInfo *ctrl)
{
volatile uint32_t status = 0;
volatile uint32_t temp;
volatile uint32_t i = 0, i_max = 0;
volatile unsigned char *dst_bfr = hsmmcsd_buffer;

while (1)
{
status = HSMMCSDStatusGet();

if (status & HS_MMCSD_STAT_BUFRDRDY)
{
HSMMCSDIntrStatusClear(ctrlInfo.memBase,
HS_MMCSD_STAT_BUFRDRDY);

if (dst_bfr != NULL)
{
if (hsmmcsd_dataLen < ctrl->blocksize)
{
i_max = hsmmcsd_dataLen;
}
else
{
i_max = ctrl->blocksize;
}
/*Input data bfr will not be 4-byte aligned*/
for (i = 0; i < i_max; i += 4)
{
temp = HW_RD_REG32(ctrlInfo.memBase + MMC_DATA);
dst_bfr[i] = *((char *) &temp);
dst_bfr[i + 1] = *((char *) &temp + 1);
dst_bfr[i + 2] = *((char *) &temp + 2);
dst_bfr[i + 3] = *((char *) &temp + 3);
}
dst_bfr += i_max;
}
}

if (status & HS_MMCSD_STAT_BUFWRRDY)
{
HSMMCSDIntrStatusClear(ctrlInfo.memBase,
HS_MMCSD_STAT_BUFWRRDY);

if (hsmmcsd_buffer != NULL)
{
for (i = 0; i < hsmmcsd_dataLen; i += 4)
{
*((char *) &temp) = hsmmcsd_buffer[i];
*((char *) &temp + 1) = hsmmcsd_buffer[i + 1];
*((char *) &temp + 2) = hsmmcsd_buffer[i + 2];
*((char *) &temp + 3) = hsmmcsd_buffer[i + 3];
HW_WR_REG32(ctrlInfo.memBase + MMC_DATA, temp);
}
}
}

if (status & HS_MMCSD_STAT_DATATIMEOUT)
{
HSMMCSDIntrStatusClear(ctrlInfo.memBase,
HS_MMCSD_STAT_DATATIMEOUT);
status = 0;
xferPend = 0;
break;
}

if (status & HS_MMCSD_STAT_TRNFCOMP)
{
HSMMCSDIntrStatusClear(ctrlInfo.memBase,
HS_MMCSD_STAT_TRNFCOMP);
status = 1;
xferPend = 0;
break;
}
}

return status;
}

The HSMMCSDStatusGet() return the MMCHS_STAT register value.

MMCHS_STAT always return zero and no condition leave the while loop.

The pins mmc1_clk and mmc1_cmd have signals and the other data pins have no signals.

Do you have any suggestions for this issue?

Thanks,

Terry

  • Hi,

    It seems that DDR is not stable. Can you run DDR stress test from PDK and ensure DDR is fine.

    Can you also update the pin mux for SD card.

    Regards,

    Rishabh

  • Hi Rishabh,

    I run the DDR stress test and it is fine.

    Where do I update the pin mux for SD card  if the board is designed follow the ti evm?.

    DDR test log:

    --------------------------------------------------------------------------------------------------------------

    DDR Stress Test Application
    Enter any character for User Input else wait for few secs for AutoRun Option
    UART read timeout (10 sec). Enable Auto Run !!
    DDR test - EMIF1
    ********************************************************
    Running DDR test case 1-- Full memory read/write
    Size of DDR is 0x1FFFFFFF
    dst address 0x81FFF000
    dst address 0x83FFE000
    dst address 0x85FFD000
    dst address 0x87FFC000
    dst address 0x89FFB000
    dst address 0x8BFFA000
    dst address 0x8DFF9000
    dst address 0x8FFF8000
    dst address 0x91FF7000
    dst address 0x93FF6000
    dst address 0x95FF5000
    dst address 0x97FF4000
    dst address 0x99FF3000
    dst address 0x9BFF2000
    dst address 0x9DFF1000
    dst address 0x9FFF0000
    DDR-- Full memory read/write test is complete
    ****************************************************************
    Running DDR test case 2 -- Random memory read/write
    Random DDR address 0x87C63000 size :0x1000
    Random DDR address 0x889D3000 size :0x1000
    Random DDR address 0x89744000 size :0x1000
    Random DDR address 0x8A4B4000 size :0x1000
    Random DDR address 0x8B224000 size :0x1000
    Test count number 0x0
    Test count number 0x1
    DDR-- Random memory read/write test is complete
    ****************************************************************
    Running DDR test case 3 -- Sequential memory read/write
    Test count number 0x0
    Test count number 0x1
    DDR-- Sequential memory read/write test is complete
    ==============================================================
    ****************************************************************
    Running DDR test case 4 -- Sequential increment pattern
    Test count number 0x0
    Test count number 0x1
    DDR-- Sequential increment pattern test is complete
    ==============================================================
    DDR test - EMIF2
    ********************************************************
    Running DDR test case 1-- Full memory read/write
    Size of DDR is 0x1FFFFFFF
    dst address 0xA1FFD001
    dst address 0xA3FFA002
    dst address 0xA5FF7003
    dst address 0xA7FF4004
    dst address 0xA9FF1005
    dst address 0xABFEE006
    dst address 0xADFEB007
    dst address 0xAFFE8008
    dst address 0xB1FE5009
    dst address 0xB3FE200A
    dst address 0xB5FDF00B
    dst address 0xB7FDC00C
    dst address 0xB9FD900D
    dst address 0xBBFD600E
    dst address 0xBDFD300F
    dst address 0xBFFD0010
    DDR-- Full memory read/write test is complete
    ****************************************************************
    Running DDR test case 2 -- Random memory read/write
    Random DDR address 0x9F742000 size :0x1000
    Random DDR address 0x9F8E0000 size :0x1000
    Random DDR address 0x9FA7E000 size :0x1000
    Random DDR address 0x9FC1B000 size :0x1000
    Random DDR address 0x9FDB9000 size :0x1000
    Test count number 0x0
    Test count number 0x1
    DDR-- Random memory read/write test is complete
    ****************************************************************
    Running DDR test case 3 -- Sequential memory read/write
    Test count number 0x0
    Test count number 0x1
    DDR-- Sequential memory read/write test is complete
    ==============================================================
    ****************************************************************
    Running DDR test case 4 -- Sequential increment pattern
    Test count number 0x0
    Test count number 0x1
    DDR-- Sequential increment pattern test is complete
    ==============================================================
    DDR Stress Test Pass
  • Hi,

    Have you used a different DDR part as compared to EVM?

    Regards,

    Rishabh

  • Hi,

    We use 2 x K4B2G1646F at EMIF1 different form ti EVM.

    DDR total size is 512MB.

    Regards,

    Terry

  • Hi Terry,

    I will ping DDR HW expert for help on DDR HW leveling timeout issue.

    Regards,

    Rishabh