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DM355-270 and 270 MHz

Other Parts Discussed in Thread: TMS320DM355

We use DM355-270 version of the chip working on 270 MHz.  We configure PLL accordingly document TMS320DM355 DMSoC 3.5.4 Supported Clocking Configurations for DM355-270, p71 for different frequencies. There are a lot issues. On 270 MHz even the kernel could not be unzipped. On other frequencies between 216 and 270 there issues with video procession.
What should we do for proper frequency configuration?

  • Aside from the PLL settings you have already verified, in a instability situation like this the next things I would look at would be the cleanliness of the clock signal and the voltage rails, just to ensure everything is up to the specs. In this device the DDR PLL is seperate from the CPU PLL so that should be remaining stable, but ensuring that the memory interface is functioning within specs is another area I would typically look at in such a case. Is this happening on just one particular board or do you have multiple instances of this issue?

    Beyond this you may also want to ensure that you actually have a DM355-270, as I understand this speed grade of these devices is in high demand and can be rare, so you may want to confirm with your authorized distributor that you are getting the 270MHz parts.

  • Thank you.
    I going to configure SDRAM Timing Register (SDTIMR).