AM3356: DDR CKE questions

user1201164

Part Number: AM3356

HI,

Our customer is verifying DDR3 with AM3356BZCZ60.
When SI analysis was performed before, all the signal lines were the same, so the same adjustment was done.
However, in order to use low-power mode with AM335x, it is necessary to re-examine the fact that it is necessary to pull-down the CKE signal (e2e.ti.com/.../638781).

Q1.
Only the CKE signal is different from other signals. How do they perform signal validation?
(Can they adjust the amplitude and delay from the CKE waveform?)

Q2.
Is it necessary to make the CKE pattern the same length as other control signals?

Best Regards,

Kouji Nishigata

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

Hi,

Q1: No, CKE amplitude and delay cannot be adjusted.
Q2: Yes, CKE belongs to the Address/Control net class.

0 user1201164 over 6 years ago in reply to Biser Gatchev-XID

Expert 1770 points

Hi,Biser

Thank you for answering

Additional questions about Q1

Can they adjust other signals independently of the CKE signal?
Or will it be adjusted to match the timing of CKE?

Best Regards,
Kouji Nishigata

0 Biser Gatchev-XID over 6 years ago in reply to user1201164

TI__Guru**** 393215 points

user1201164 said:
Can they adjust other signals independently of the CKE signal?

No.

user1201164 said:
Or will it be adjusted to match the timing of CKE?

Yes.

0 user1201164 over 6 years ago in reply to Biser Gatchev-XID

Expert 1770 points

Hi,

Thank you for answering

Is there anything like a delay standard in ADDR_CTRL net class signals?

A delay occurs because our customer processes differently only for the DDR_CKE signal. They are asking how much delay is allowed.

Best Regards,

Kouji Nishigata

0 JJD over 6 years ago in reply to user1201164

TI__Guru* 86750 points

Kouji, i don't understand your question. What is different about the CKE signal in your customer's board? As stated before, CKE is part of the ADDR_CTRL net class, so all routing guidelines should be followed for that net class.

Regards,

James

0 user1201164 over 6 years ago in reply to JJD

Expert 1770 points

Hi, James

Thank you for the response.

It differs from other ADDR_CTRL in that DDR_CLK is pulled down.
For this reason, the delay time occurs in your simulation compared to other signals.

Their question is how much is acceptable for this delay time.
Or if they follow the Routing Specification like Table 7-68 in datasheet (SPRS717K), can they ignore this delay time?

Best Regards,

Kouji Nishigata

0 JJD over 6 years ago in reply to user1201164

TI__Guru* 86750 points

Hi Kouji,

CKE is mostly a static signal, high during normal mode of operation, and low during self refresh. A lot of the timing is controlled by the controller. You should have to worry about the effect of the pull down resistor.

Regards,

James

0 user1201164 over 6 years ago in reply to JJD

Expert 1770 points

Hi,James

Thank you for the answer.

CKE is not as active as other signal lines, but DDR (DDR3) seems to be judged at the rising edge of CK.
For this reason, the delay time of CK and CKE should eventually become a problem.
In response to “You should have to worry about the effect of the pull-down resistor”, they are asking what criteria they should design.
Do they have to adjust the pull down resistor and the wiring length until the delay time becomes zero?

Best Regards,

Kouji Nishigata

0 JJD over 6 years ago in reply to user1201164

TI__Guru* 86750 points

Kouji, no, they do not need to adjust for delay times between CKE and CK. See StarterKit EVM as an example. We used a 10K pull down on CKE.

Regards,

James

0 user1201164 over 6 years ago in reply to JJD

Expert 1770 points

Hi,James

Thank you for the answer.

If the pull-up resistance is 10kΩ and they are wired according to the “CK and ADDR_CTRL Routing Specification” in the data sheet,

they don't need to worry about the CKE's delay time.

Is my understanding correct?

Best Regards,

Kouji Nishigata

0 JJD over 5 years ago in reply to user1201164

TI__Guru* 86750 points

Kouji, that is correct

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AM3356: DDR CKE questions