• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 759 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[TDA4M] Request high speed impedance line design guide in TDA4M Processor. (MIPI CSI, SGMII, RGMII, USB, DP, MMC etc..)

Jinyoung Park
Prodigy 210 points

Hi
I am glad to receive the LPDDR4 design guide file. I used it well for this artwork.

However, I haven't found any other high-speed impedance line (MIPI, SGMII, RGMII, USB, DP etc) design guides.

Currently, the following documents are referred to.

   High-Speed Layout Guidelines for Signal Conditioners  and USB Hubs (SLLA414–August 2018)

 

I have some questions.

1. Is there no need for length matching of TX group and Rx group in RGMII Interface?

2. Do Tx_Pair, Rx_Pair, and Ref.CLK_Pair only match intra-pair-skew in SGMII Interface?

Is there a maximum allowance for inter-pair-skew?

Should I place the AC coupled Capacitors close to the Transmitters?

3. Does Intra-pair-skew need to be length matched in DP (Display port) and USB3.0? What is the maximum allowable length of inter-pair-skew?

  • 0
    TI__Guru 52065 points

    1.  Yes, RGMII interface needs to be skew controlled.  The transmit interface is latched relative to TXC, all Transmit signals (TX_CTL, TD[3:0] need to be skew matched with TXC.  Similar with receive interface.  All receive signals are latched relative to RXC, thus all receive signals (RX_CTL, RD[3:0] need to be skew matched with RXC.  No need to control skew between transmit and receive signals.

    2. Yes - SGMII signals only need to be skew matched intra-pair (+ and -).  Recommend skew is less than/equal 2ps.  No need to skew control between TX, RX, and CLK.  It is not that critical where AC-coupled capacitors are located. Recommend placing where PCB routing is best optimized.

    3.  Yes - both USB3 and DP should be intra-pair skew controlled (+ and -) to less than/equal 1ps.

  • 0 in reply to Robert Eschler
    Prodigy 210 points

    I understood that I had to satisfy the "intra-pair skew" on the DP interface.

    Should I not consider inter-pair skew on DP interface?

  • 0 in reply to Jinyoung Park
    TI__Guru 52065 points

    The DisplayPort spec for the transmitter states the skew across all lanes should be less than 1250ps.  I recommend a value less than the spec, as it should be easily achievable in the design.