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AM5716: GMAC switch port speed

Stephen Turner
Genius 3476 points
Part Number: AM5716

The AM57xx family has two Gb ethernet ports. 

The ports (Port1 and Port2)are connected internally to a switch (GMAC_SW) and the processor transfers data through this switch on Port0. 

Can each port be operated simultaneously at the full 1Gbs bandwidth or is the bandwidth halved when both are used at the same time?

  • 0
    TI__Mastermind 27890 points

    Hi, sorry for the delay. We are discussing this internally (HW team + SW team) and will have something more for you soon.

  • 0 in reply to -DK-
    TI__Mastermind 40080 points

    Hi,

    Internally the packets move within the switch at close to line rate. I am not sure if I am following your question though, so I am assuming you are asking about packets going into DDR and being processed by the ARM. The external packets destined for port 0 will exit to DDR via a DMA engine, there will be some/slight loss here as the DMA engine competes for the internal bus with other peripherals. The larger loss will be the ARM processing the packets as it competes with other OS and application threads.

    With Linux as the OS here is a Link on UDP packet ingress. The link below shows the bit rate based on different packet sizes. To qualify the test in a little more detail is that a couple of things to take into account. First is that most likely the sender is not able to send at line rate, the published test is based on one external port and the traffic is continuous. 

    The data I am providing also is not directly answering what you have asked about. I need to confirm this next point with the IP team as I have made the assumption here that the packet depth in the internal FIFOs in the switch negate the affect of two packets being received simultaneously on the external ports of the switch.

    UDP Packet Ingress (Look for the AM57x column)

    Best Regards,

    Schuyler

  • 0 in reply to Schuyler Patton
    TI__Mastermind 40080 points

    Hi,

    I confirmed with the ip team concerning the internal portion of the data transfer. Essentially the switch has a non-blocking fabric that can have packets received on all ports simultaneously without any effect on any other port. As I mentioned in the previous post most of the limitation will be on how fast the ARM can service the packets after they arrive in DDR.

    Hopefully this helps.

    Best Regards,

    Schuyler