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AM6527: DDR4 initialization fails

Part Number: AM6527

Currently in the board bring up process to boot Linux from SD card on the AM6527 and it is failing the DDR4 initialization portion. We are using 4x Micron MT40A1G8SA-062E 8Gb DDR4 SDRAMs single rank.

Prior to creating the build, we generated new u-boot files for the RAM using the AM65x EMIF V1.95 worksheet with our configurations and timing parameters, then built our Linux image with it. Booting from the SD card failed, so we removed it and tried to initialize the DDR4 using the EMIF generated GEL file and the GELs in CCS.  We're on CCS9.1.0.00010 and using XDS560V2 emulator.

After running the DDR_Initialization script on the Cortex R5, we get a write leveling adjustment failure and the CCS debug console reads:

MCU_PULSAR_Cortex_R5_0: GEL Output:
Waiting for Write leveling adjustment to complete
MCU_PULSAR_Cortex_R5_0: GEL Output:
Write leveling adjustment done
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x808000FF
MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling Adjustment Training****
MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling Adjustment status per byte...
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX0RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX1RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX2RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX3RSR2 = 0x00000001
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX4RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX0RSR3 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX1RSR3 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX2RSR3 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX3RSR3 = 0x00000001
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX4RSR3 = 0x00000000

Which shows that the Write Leveling Adjustment is failing on Byte Lane 3

As a check, we changed the DDR Total Data Bus Width in the EMIF from 32 to 16 and that initialization was successful. We then ran Data_WrRd_test (modified for x16 memory addressing), and that passed as well. This indicates that the DDR device on Byte lane 3 is somehow not initializing correctly while devices on byte lane 0 and 1 are initializing fine.

What is Write Leveling Adjustment and how is it different from Write Leveling training? We notice that when initializing x32 bus width, the write leveling training is successful while the adjustment fails.

Are there any additional registers that we can read/access that gives us more information that may help us identify if we have PCB layout problems?

If we can't initialize x32 bus width DDR4, what do we need to modify in order to boot Linux using a x16 bus width configuration besides the EMIF?

Thank you,

Eric

  • The EMIF and the data sheet for the DDR4 are in the attached .zip file.

    The only thing we changed in the EMIF when we tried to initialize x16 bus width is the DDR Total Bus Width parameter on Sheet1, step 1A, from 32 to 16. All other parameters remained the same.AM65x_DRA80xM_EMIF_Tool_1.95 (Modified for Smart Board DDR).xlsm.zip

  • Eric, write leveling adjustment is an extra training step the controler uses to find extra clock cycles need to be added in the write path because of board delays.  

    I noticed a few edits which need to be made to your spreadsheet.  Can you make these adjustments and try again:

    CAS_Latency = 11 

    CWL = 9

    The values above are taken from the DDR4-3200 Speed Bin Table in the DDR datasheet.  Since you will be operating the at DDR4-1600, use the values in the row associated with this max data rate.  I think this may be contributing to the errors you are seeing with WLA.

    I double checked the rest of your DDR timings in the spreadsheet (i don't think any of these are related to your error, just double checking everything else).  Here are some more edits i found

    tDLLK = 1024 tCK

    tCAL = 6 tCK

    tPAR_ALERT_PW(max) = 192

    Regards,

    James

  • Thanks James! The DDR Initialization passed with the suggested values. We'll now attempt to include to the .dtsi with the corrected timing parameters in our build so that we can try and boot from the SD card.

  • James,

    Using the suggested parameters above, I can successfully generate a GEL file using the EMIF tool.

    However, when I try to generate the u-boot .dtsi file, something goes wrong in the excel and row 91 in the u-boot sheet gives me an error:

    # define DDRSS_DDRPHY_DTPR2 #NUM!

    This happens when the tDLLK parameter is changed from 768 to 1024. The .dtsi is generated without issue when tDLLK is set to 768.

    Is there a bug in the EMIF?

  • Hi Eric, after reviewing the DDR datasheet more, there is a note pertaining to tDLLK:

    2. tCCD_L and tDLLK should be programmed according to the value defined per operating
    frequency. Micron tDLLK values support the legacy JEDEC tDLLK specifications.


    So i think the tDLLK min should correspond to the operating frequency value, which for DDR4-1600 is 597.  This should fix the issue you are seeing

    Regards,

    James

  • Hi James,

    The .dtsi file generates correctly when tDLLK is set properly.

    Oddly enough, I can't seem to get the DDR to initialize correctly using the GEL files now, even when I revert back to the original suggested values.

    It is failing at WLA for byte lane 3 again. The EMIF I am using is attached.

    EDIT: Even though the WLA and the initialization failed, it still passes the Data WrRd test in the DDR Testing portion of the scripts

    EricAM65x_DRA80xM_EMIF_Tool_1.95 (Modified for Smart Board DDR) 1.xlsm.zip

  • Hi Eric, does this problem show up on multiple boards, or or you just testing on one?  You may want to check voltage levels associated with DDR, especially with VTT voltages

    The Data WrRd test is very basic, just performing 32-bit read/writes single access, so i don't think that is telling you much.  You might also want to check the layout associated with byte 3, and be sure the design conforms to the design guidelines from this app note: 

      Regards,

    James

  • James,

    Voltage reading on VTT revealed that it was way out of spec due to a PCB error. We fixed it and now the DDR initializes!

    Thanks, Eric

  • Good to hear, Eric.  Thanks for the confirmation.

    Regards,

    James