Part Number: AM6527
Currently in the board bring up process to boot Linux from SD card on the AM6527 and it is failing the DDR4 initialization portion. We are using 4x Micron MT40A1G8SA-062E 8Gb DDR4 SDRAMs single rank.
Prior to creating the build, we generated new u-boot files for the RAM using the AM65x EMIF V1.95 worksheet with our configurations and timing parameters, then built our Linux image with it. Booting from the SD card failed, so we removed it and tried to initialize the DDR4 using the EMIF generated GEL file and the GELs in CCS. We're on CCS9.1.0.00010 and using XDS560V2 emulator.
After running the DDR_Initialization script on the Cortex R5, we get a write leveling adjustment failure and the CCS debug console reads:
MCU_PULSAR_Cortex_R5_0: GEL Output:
Waiting for Write leveling adjustment to complete
MCU_PULSAR_Cortex_R5_0: GEL Output:
Write leveling adjustment done
MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x808000FF
MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling Adjustment Training****
MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling Adjustment status per byte...
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX0RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX1RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX2RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX3RSR2 = 0x00000001
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX4RSR2 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX0RSR3 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX1RSR3 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX2RSR3 = 0x00000000
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX3RSR3 = 0x00000001
MCU_PULSAR_Cortex_R5_0: GEL Output:
DDRSS_DDRPHY_DX4RSR3 = 0x00000000
Which shows that the Write Leveling Adjustment is failing on Byte Lane 3
As a check, we changed the DDR Total Data Bus Width in the EMIF from 32 to 16 and that initialization was successful. We then ran Data_WrRd_test (modified for x16 memory addressing), and that passed as well. This indicates that the DDR device on Byte lane 3 is somehow not initializing correctly while devices on byte lane 0 and 1 are initializing fine.
What is Write Leveling Adjustment and how is it different from Write Leveling training? We notice that when initializing x32 bus width, the write leveling training is successful while the adjustment fails.
Are there any additional registers that we can read/access that gives us more information that may help us identify if we have PCB layout problems?
If we can't initialize x32 bus width DDR4, what do we need to modify in order to boot Linux using a x16 bus width configuration besides the EMIF?
Thank you,
Eric