Hi all,
The EMIF tool
is not compatible with the last PLSDK 6.0.0.7. The emif tool can work with PLSDK 5.0.0.15.
Do you have any suggestion about this?
thanks!
BR,
Denny
Hi, James:
We use the EMIF Tools and file in the spec of DDR3L chip and our layout information to generate the uboot registers configuration as bellow:(the file also attached in Denny's question)
/* =========================================================================
* Copyright (C) 2017 Texas Instruments Incorporated
*
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
* The program may not be used without the written permission
* of Texas Instruments Incorporated or against the terms and conditions
* stipulated in the agreement under which this program has been
* supplied.
* ========================================================================= */
/*
* AM574x_DDR3L_666MHz_NOM-R002_config.c
* Created on: 09/11/2019
* Created with: EMIF_RegisterConfig_v2.0.2
*/
#include "emif4d5_wrapper.h"
const struct dpll_params AM574x_DDR3L_666MHz_NOM-R002_pll_params = {
.m = 333,
.n = 4,
.m2 = 2,
.m4_h11 = 8
}; // can not be found the struct in borad.c and para are not same
const struct ctrl_ioregs AM574x_DDR3L_666MHz_NOM-R002_ctrl_ioregs = {
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrch = 0x40404040,
.ctrl_ddrio_0 = 0x00094A40,
.ctrl_ddrio_1 = 0x00000000,
.ctrl_emif_sdram_config_ext = 0x0001C123
}; // can not be found the struct in borad.c
const struct dmm_lisa_map_regs AM574x_DDR3L_666MHz_NOM-R002_dmm_regs = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
const struct emif_regs AM574x_DDR3L_666MHz_NOM-R002_emif_regs = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD33367EC,
.sdram_tim2 = 0x30B37FE3,
.sdram_tim3 = 0x409F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400E,
.emif_ddr_phy_ctlr_1 = 0x0E24400E,
.emif_rd_wr_exec_thresh = 0x00000305,
.emif_ecc_ctrl_reg = 0xC0000001,
.emif_ecc_address_range_1 = 0x1FFF0000,
.emif_ecc_address_range_2 = 0x00000000,
};
/*
* DLL Ratio Values are an estimate based on trace lengths. Either
* software leveling or hardware leveling should be performed to
* determine final DLL values.
*/
const unsigned int AM574x_DDR3L_666MHz_NOM-R002_emif1_ext_phy_regs [] = {
0x04040100, // EMIF1_EXT_PHY_CTRL_1
0x006B0093, // EMIF1_EXT_PHY_CTRL_2
0x006B0098, // EMIF1_EXT_PHY_CTRL_3
0x006B009A, // EMIF1_EXT_PHY_CTRL_4
0x006B0096, // EMIF1_EXT_PHY_CTRL_5
0x006B009B, // EMIF1_EXT_PHY_CTRL_6
0x002F002F, // EMIF1_EXT_PHY_CTRL_7
0x002F002F, // EMIF1_EXT_PHY_CTRL_8
0x002F002F, // EMIF1_EXT_PHY_CTRL_9
0x002F002F, // EMIF1_EXT_PHY_CTRL_10
0x002F002F, // EMIF1_EXT_PHY_CTRL_11
0x00600071, // EMIF1_EXT_PHY_CTRL_12
0x0060006D, // EMIF1_EXT_PHY_CTRL_13
0x0060006A, // EMIF1_EXT_PHY_CTRL_14
0x0060006F, // EMIF1_EXT_PHY_CTRL_15
0x00600078, // EMIF1_EXT_PHY_CTRL_16
0x00400051, // EMIF1_EXT_PHY_CTRL_17
0x0040004D, // EMIF1_EXT_PHY_CTRL_18
0x0040004A, // EMIF1_EXT_PHY_CTRL_19
0x0040004F, // EMIF1_EXT_PHY_CTRL_20
0x00400058, // EMIF1_EXT_PHY_CTRL_21
0x00800080, // EMIF1_EXT_PHY_CTRL_22
0x00800080, // EMIF1_EXT_PHY_CTRL_23
0x40010080, // EMIF1_EXT_PHY_CTRL_24
0x08102040, // EMIF1_EXT_PHY_CTRL_25
0x00000083, // EMIF1_EXT_PHY_CTRL_26
0x00000088, // EMIF1_EXT_PHY_CTRL_27
0x0000008A, // EMIF1_EXT_PHY_CTRL_28
0x00000086, // EMIF1_EXT_PHY_CTRL_29
0x0000008B, // EMIF1_EXT_PHY_CTRL_30
0x00000041, // EMIF1_EXT_PHY_CTRL_31
0x0000003D, // EMIF1_EXT_PHY_CTRL_32
0x0000003A, // EMIF1_EXT_PHY_CTRL_33
0x0000003F, // EMIF1_EXT_PHY_CTRL_34
0x00000048, // EMIF1_EXT_PHY_CTRL_35
0x00000077 // EMIF1_EXT_PHY_CTRL_36
}; // 36 registers
const unsigned int AM574x_DDR3L_666MHz_NOM-R002_emif2_ext_phy_regs [] = {
0x04040100, // EMIF2_EXT_PHY_CTRL_1
0x006B0095, // EMIF2_EXT_PHY_CTRL_2
0x006B0090, // EMIF2_EXT_PHY_CTRL_3
0x006B0095, // EMIF2_EXT_PHY_CTRL_4
0x006B0090, // EMIF2_EXT_PHY_CTRL_5
0x006B006B, // EMIF2_EXT_PHY_CTRL_6
0x002F002F, // EMIF2_EXT_PHY_CTRL_7
0x002F002F, // EMIF2_EXT_PHY_CTRL_8
0x002F002F, // EMIF2_EXT_PHY_CTRL_9
0x002F002F, // EMIF2_EXT_PHY_CTRL_10
0x002F002F, // EMIF2_EXT_PHY_CTRL_11
0x0060006A, // EMIF2_EXT_PHY_CTRL_12
0x0060006E, // EMIF2_EXT_PHY_CTRL_13
0x00600069, // EMIF2_EXT_PHY_CTRL_14
0x0060006E, // EMIF2_EXT_PHY_CTRL_15
0x00600060, // EMIF2_EXT_PHY_CTRL_16
0x0040004A, // EMIF2_EXT_PHY_CTRL_17
0x0040004E, // EMIF2_EXT_PHY_CTRL_18
0x00400049, // EMIF2_EXT_PHY_CTRL_19
0x0040004E, // EMIF2_EXT_PHY_CTRL_20
0x00400040, // EMIF2_EXT_PHY_CTRL_21
0x00800080, // EMIF2_EXT_PHY_CTRL_22
0x00800080, // EMIF2_EXT_PHY_CTRL_23
0x40010080, // EMIF2_EXT_PHY_CTRL_24
0x08102040, // EMIF2_EXT_PHY_CTRL_25
0x00000085, // EMIF2_EXT_PHY_CTRL_26
0x00000080, // EMIF2_EXT_PHY_CTRL_27
0x00000085, // EMIF2_EXT_PHY_CTRL_28
0x00000080, // EMIF2_EXT_PHY_CTRL_29
0x00000000, // EMIF2_EXT_PHY_CTRL_30
0x0000003A, // EMIF2_EXT_PHY_CTRL_31
0x0000003E, // EMIF2_EXT_PHY_CTRL_32
0x00000039, // EMIF2_EXT_PHY_CTRL_33
0x0000003E, // EMIF2_EXT_PHY_CTRL_34
0x00000000, // EMIF2_EXT_PHY_CTRL_35
0x00000077 // EMIF2_EXT_PHY_CTRL_36
}; // 36 registers
struct emif_cfg AM574x_DDR3L_666MHz_NOM-R002 = {
.platform = "AM574x_DDR3L_666MHz_NOM-R002",
.EMIF2_DEFINED = 1,
.pll_regs = &AM574x_DDR3L_666MHz_NOM-R002_pll_params,
.ctrl_regs = &AM574x_DDR3L_666MHz_NOM-R002_ctrl_ioregs,
.dmm_regs = &AM574x_DDR3L_666MHz_NOM-R002_dmm_regs,
.regs = &AM574x_DDR3L_666MHz_NOM-R002_emif_regs,
.phy_regs1 = AM574x_DDR3L_666MHz_NOM-R002_emif1_ext_phy_regs,
.phy_regs2 = AM574x_DDR3L_666MHz_NOM-R002_emif2_ext_phy_regs,
};
And now, we use SDK 6.0.0.7 and found board.c in u-boot-2019.01+gitAUTOINC+8b90adfb16-g8b90adfb16\board\ti\am57xx
static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
.dmm_lisa_map_3 = 0x80740300,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
.dmm_lisa_map_3 = 0x80640100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
.dmm_lisa_map_2 = 0xc0600200,
.dmm_lisa_map_3 = 0x80600100,
.is_ma_present = 0x1
};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
if (board_is_am571x_idk())
*dmm_lisa_regs = &am571x_idk_lisa_regs;
else if (board_is_am574x_idk())
*dmm_lisa_regs = &am574x_idk_lisa_regs;
else
*dmm_lisa_regs = &beagle_x15_lisa_regs;
}
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xcccf36ab,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x409f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x10040100,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00340034,
0x00350035,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0
}; // Only 35 registers and are not matched with EMIF Tools
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xcccf36b3,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x407f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
0x10040100,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00340034,
0x00350035,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0
}; // Only 35 registers and are not matched with EMIF Tools
static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
.sdram_config_init = 0x61863332,
.sdram_config = 0x61863332,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x0000514d,
.ref_ctrl_final = 0x0000144a,
.sdram_tim1 = 0xd333887c,
.sdram_tim2 = 0x30b37fe3,
.sdram_tim3 = 0x409f8ad8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400f,
.emif_ddr_phy_ctlr_1 = 0x0e24400f,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100, // not included in EMIF TOOLS
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
.sdram_config_init = 0x61863332,
.sdram_config = 0x61863332,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x0000514d,
.ref_ctrl_final = 0x0000144a,
.sdram_tim1 = 0xd333887c,
.sdram_tim2 = 0x30b37fe3,
.sdram_tim3 = 0x409f8ad8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400f,
.emif_ddr_phy_ctlr_1 = 0x0e24400f,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100, // not included in EMIF TOOLS
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305,
.emif_ecc_ctrl_reg = 0xD0000001,
.emif_ecc_address_range_1 = 0x3FFF0000,
.emif_ecc_address_range_2 = 0x00000000
};
So we don't know how to initial our DDR3L successfully.
Do you have the newest EMIF TOOL that compatible with the lastest SDK?
Another question is :
We use 2 chips of 512MB DDR3L in EMIF1 and 1 chip of 512MB in ECC,
2 chips of 512MB DDR3L in EMIF2
So what the reasonable the ECC Region 1: System End Address ? 9FFFFFFF or BFFFFFFF
Thank you so much.
