Hi,
1. According to documentation, BAR0 register is fixed to be mapped to the PCIe application registers region. Does this apply for RC and EP also on C66x devices?
2. According to documentation, BAR0 cannot be remapped to any other location than the application registers, starting from 0x2180_0000 in C6678 devices. Does this mean the ibCfg.ibOffsetAddr could be set with 0 if inbound translation is used for BAR0? For generating MSI it could simply write *((volatile uint32_t *)0x60000054) = msi_id ?
Details:
RC:
#define PCIE_OB_LO_ADDR_RC 0x70000000
#define PCIE_OB_HI_ADDR_RC 0x0
#define PCIE_OB_REGION_RC 0 // region 0
pcieObTransCfg (handle, PCIE_OB_LO_ADDR_RC, PCIE_OB_HI_ADDR_RC, PCIE_OB_REGION_RC)
EP:
#define PCIE_BAR_IDX_EP 0 // BAR0
#define PCIE_IB_LO_ADDR_EP 0x70000000
#define PCIE_IB_HI_ADDR_EP 0x0
#define PCIE_IB_REGION_EP 0
ibCfg.ibBar = PCIE_BAR_IDX_EP; /* Match BAR that was configured above*/
ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_EP;
ibCfg.ibStartAddrHi = PCIE_IB_HI_ADDR_EP;
ibCfg.ibOffsetAddr = 0; // ????
ibCfg.region = PCIE_IB_REGION_EP;
pcieIbTransCfg(handle, &ibCfg));
To generate MSI from RC to EP: *((volatile uint32_t *)0x60000054) = msi_id
Is this ok as inbound is already aligned to start address 0x2180_0000 when mapped to BAR0?
I know that it may not need to configure inbound registers for BAR0, but I am interested by the case when I want to do this....
Thank you.
