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AM4378: GP EVM power-down sequencing

Part Number: AM4378
Other Parts Discussed in Thread: TPS65218, TPS65218D0

Hi,

Is the power down sequence supported with AM437x EVM?

What are the conditions under which the TPS65218 power down sequence starts when the main power is turned off?

Is it assumed that TPS65218 OFFnPFO bit is set by software?
Is the power down sequence activated under the condition VIN_BIAS <VUVLO when the main power is turned off?

Our customer is designing with reference to AM427x EVM schematic.
When the main power is turned off, they are wondering whether the current AM437x EVM schematic is a schematic in which the power-down sequence runs.

Best Regards,
Shigehiro Tsuda

  • Is the power down sequence supported with AM437x EVM?


    Yes the TPS65218D0 handles all the power sequencing.

    What are the conditions under which the TPS65218 power down sequence starts when the main power is turned off?


    This information can be found in the datasheet section 5.3.1.2. The EVM uses PMIC_POWER_EN / PWR_EN handshake to shutdown.

    Is it assumed that TPS65218 OFFnPFO bit is set by software?


    The Power Fail Comparator (PFO) is an optional feature of the PMIC that can be used to emergency shutdown in response to system supply voltage changes. It is up to software to set the control bit. This shutdown method provides no warning to software but it uses the proper hardware power down sequence. I do not know if software will set this bit.

    Is the power down sequence activated under the condition VIN_BIAS < VUVLO when the main power is turned off? Our customer is designing with reference to AM427x EVM schematic. When the main power is turned off, they are wondering whether the current AM437x EVM schematic is a schematic in which the power-down sequence runs.


    It's not clear based on the description from datasheet section 5.3.1.2 what the UVLO behavior is. Please ask this question on the PMIC forum. I see the following notes in the datasheet that are not clear.

    A power-down sequence executes if a fault occurs in the IC (OTS, UVLO, PGOOD failure).

    If the supply voltage on IN_BIAS drops below 2.5 V, the digital core is reset and all power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and LDO1).
    When system power fails, the UVLO comparator triggers the power-down sequence. If system power drops below 2.5 V, the digital core is reset and all remaining power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and LDO1).

    I think since the UVLO is adjustable, it will trigger the power down sequence if the UVLO is crossed while the UVLO is > 2.5V. If the supply is below 2.5V then there is an emergency shutdown with all supplies at once.

  • Hi Ahmad,

    Thank you for quick reply.

    The PMIC_POWER_EN control does not satisfy the power-down sequence condition when the hardware power is turned off because the software must operate.
    I will check it in PMIC Forum.

    Best Regards,
    Shigehiro Tsuda

  • Correct the PMIC_POWER_EN control requires software to operate. So the UVLO might perform the sequence if you can get confirmation from the PMIC team.

  • Hi Ahmad,

    Thank you for quick reply and kindly support.
    I understand it by your answer.

    Best Regards,
    Shigehiro Tsuda