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TMS320C6748: UART RX+EDMA+Rx timeout Interrupt

Part Number: TMS320C6748

Hi,

I'm trying to receive an unknown length data over UART by EDMA. Basically, Is it possible by using RX-Timeout interrupt?

To do it, I wrote the following code (pseue-code) :

#define UART_RX_EDMA_LEN 64
#define UART_RX_TRIG_LEN 8

uint8 uart_rx_buff[8KB];
uint32 uart_rx_buff_cnt = 0;

uint8 edma_uart_rx_buff[UART_RX_EDMA_LEN];

uart_init(){
 uart_enable_interrupt(UART_INT_RHR_RX_TIME_OUT); //Set IER
 uart_fifo_configure(UART_RX_TRIG_LEN, UART_TX_TRIG_LEN ); // Set UART RX/TX FIFO trigger threshold
 ...
}

start_uart_receive(){
 edma_rx_param_set.src = edma_uart_rx_buff;
 edma_rx_param_set.aCnt = 1;
 edma_rx_param_set.bCnt = UART_RX_TRIG_LEN;
 edma_rx_param_set.cCnt = UART_RX_EDMA_LEN / UART_RX_TRIG_LEN;
 edma_rx_param_set.opt = (1 << EDMA3CC_OPT_SYNCDIM_SHIFT);
 edma_rx_param_set.opt |= ((edmaUartnRxTccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
 edma_rx_param_set.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
...
}

edma_uart_rx_isr(){
 memcpy(uart_rx_buff[uart_rx_buff_cnt], edma_uart_rx_buff, UART_RX_EDMA_LEN);
 uart_rx_buff_cnt += UART_RX_EDMA_LEN;
}

uart_isr(){
uint8 interrupt_src = uart_get_int_src(); // Get IIR
if(interrupt_src == UART_SRC_INT_RX_TIME_OUT){
  EdmaParamSet edma_param_set_uart_rx;
  uint8 uart_fifo_chars[UART_RX_TRIG_LEN];
  uint32 uart_fifo_length;
  edma_get_paramset(edmaUartnRxTccNum, &edma_param_set_uart_rx);
  uint32 edma_uart_recvd_len = UART_RX_EDMA_LEN - edma_param_set_uart_rx.bCnt * edma_param_set_uart_rx.cCnt;
  memcpy(uart_rx_buff[uart_rx_buff_cnt], edma_uart_rx_buff, edma_uart_recvd_len); //Appends not completed EDMA transfer data
  uart_rx_buff_cnt += edma_uart_recvd_len;
  uart_fifo_length = uart_read_fifo(uart_fifo_chars);
  memcpy(uart_rx_buff[uart_rx_buff_cnt], uart_fifo_chars, uart_fifo_length); //Appends FIFO chars
  uart_rx_buff_cnt += uart_fifo_length;
  uart_rx_receive_cb(uart_rx_buff, uart_rx_buff_cnt);
}
}

According to the device TRM, setting `RHRIT` bit in IER register, causes enabling two interrupt: RHR interrupt and RX-Timeout interrupt.

But there are some unusual behaviors during sending data to the device UART.

1) When sent data length is a multiple of `UART_RX_TRIG_LEN`(=8), (8, 16, 24,...) Rx timeout interrupt does not occurs! and an unusual interrupt occurs with IER.IT_TYPE = 0! In the TRM mentioned that it is a Modem Interrupt. While MSR did not change and I expected IER.IT_TYPE = 6 or 2.
2) When sent data length is higher than 8, multiple interrupts occurs, some Modem-Interrupt (Data length / 8 times with unchanged MSR like the case 1)  in addition with a RX-Timeout interrupt at the end.
3) When sent data length is lower than `UART_RX_TRIG_LEN`(=8), Rx timeout interrupts occurs successfully.

Cases 2 and 3 are acceptable, but in case 1 , I can not detect end of data.
TIA!

  • Hello,

    Could you please share which software package you are using and if this is based on one of our examples?

    There were some threads with discussion of this topic. Could you please take a look?

    https://e2e.ti.com/support/processors/f/791/t/317229

    https://e2e.ti.com/support/processors/f/791/t/384458?C6748-UART-driver-using-EDMA-for-higher-performance

    https://e2e.ti.com/support/processors/f/791/t/324489?C6742-C6746-C6748-UART-and-EDMA-considerations

    https://e2e.ti.com/support/processors/f/791/p/398100/1408537

    Also, there is a UART + EDMA example inside the Starterware package that may be of help as well. I've attached it below for your reference.

    /**
     * \file  uartEcho.c
     *
     * \brief This is a sample application file which invokes some APIs
     *        from the EDMA3 device abstraction layer as well as UART 
     *        device abstraction layer to perform configuration, and 
     *        transfer of data between UART and CPU RAM by the 
     *        use of EDMA3
     */
    
    /*
    * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 
    *
    *  Redistribution and use in source and binary forms, with or without 
    *  modification, are permitted provided that the following conditions 
    *  are met:
    *
    *    Redistributions of source code must retain the above copyright 
    *    notice, this list of conditions and the following disclaimer.
    *
    *    Redistributions in binary form must reproduce the above copyright
    *    notice, this list of conditions and the following disclaimer in the 
    *    documentation and/or other materials provided with the   
    *    distribution.
    *
    *    Neither the name of Texas Instruments Incorporated nor the names of
    *    its contributors may be used to endorse or promote products derived
    *    from this software without specific prior written permission.
    *
    *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
    *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
    *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
    *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
    *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    */
    
    #include "psc.h"
    #include "uart.h"
    #include "edma.h"
    #include "string.h"
    #include "hw_types.h"
    #include "uartStdio.h"
    #include "lcdkOMAPL138.h"
    #include "interrupt.h"
    #include "edma_event.h"
    #include "soc_OMAPL138.h"
    #include "hw_psc_OMAPL138.h"
    
    /****************************************************************************/
    /*                      INTERNAL MACRO DEFINITIONS                          */
    /****************************************************************************/
    #define UART_RBR_THR_REG           ((0x01D0D000u) + (0u))
    
    #define MAX_ACNT                   1
    #define MAX_CCNT                   1
    
    #define RX_BUFFER_SIZE             20
    
    /* EDMA3 Event queue number. */
    #define EVT_QUEUE_NUM	           0
    
    /****************************************************************************/
    /*                      LOCAL FUNCTION PROTOTYPES                           */
    /****************************************************************************/
    static void UartTransmitData(unsigned int tccNum, unsigned int chNum,
                                 volatile char *buffer, unsigned int buffLength);
    
    /* Callback Function Declaration*/
    static void (*cb_Fxn[EDMA3_NUM_TCC]) (unsigned int tcc, unsigned int status);
    static void UartReceiveData(unsigned int tccNum, unsigned int chNum, 
                                volatile char *buffer);
    static void callback(unsigned int tccNum, unsigned int status);
    static void ConfigureIntEDMA3(void);
    static void Edma3ComplHandlerIsr(void);
    static void Edma3CCErrHandlerIsr(void);
    static void EDMA3Initialize(void);
    static void SetupInt(void);
    
    /****************************************************************************/
    /*                      GLOBAL VARIABLES                                    */
    /****************************************************************************/
    volatile unsigned int flag = 0;
    
    /****************************************************************************/
    /*                   LOCAL FUNCTION DEFINITIONS                             */
    /****************************************************************************/
    
    /*
    ** Main function.
    */
    
    int main(void)
    {
        volatile char enter[] = "\r\nPlease Enter 20 bytes from keyboard\r\n";
        volatile char buffer[RX_BUFFER_SIZE];
        unsigned int buffLength = 0;
    
        /* Initialize EDMA3 Controller */
        EDMA3Initialize();
    
        /* Initialize UART */
        UARTStdioInit();
    
        /* Request DMA Channel and TCC for UART Transmit*/
        EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA, 
                            EDMA3_CHA_UART2_TX, EDMA3_CHA_UART2_TX,
                            EVT_QUEUE_NUM);
    
        /* Registering Callback Function for TX*/
        cb_Fxn[EDMA3_CHA_UART2_TX] = &callback; 
    
        /* Request DMA Channel and TCC for UART Receive */
        EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
                            EDMA3_CHA_UART2_RX, EDMA3_CHA_UART2_RX,
                            EVT_QUEUE_NUM);
    
        /* Registering Callback Function for RX*/
        cb_Fxn[EDMA3_CHA_UART2_RX] = &callback; 
    
        /* Used for bCnt */
        buffLength = strlen((const char *) enter); 
    
        /* Transmit Data for Enter Message */
        UartTransmitData(EDMA3_CHA_UART2_TX, EDMA3_CHA_UART2_TX,
                         enter, buffLength);
    
        /* Enabling UART in DMA Mode*/
        UARTDMAEnable(SOC_UART_2_REGS, UART_RX_TRIG_LEVEL_1 |  \
                                       UART_DMAMODE |          \
                                       UART_FIFO_MODE );
    
        /* Wait for control to return from call-back function */
        while(0 == flag); 
        flag = 0;
    
        /* Receive Data for Input */
        UartReceiveData(EDMA3_CHA_UART2_RX, EDMA3_CHA_UART2_RX, buffer);
    
    
        /* Enabling UART in DMA Mode*/
        UARTDMAEnable(SOC_UART_2_REGS, UART_RX_TRIG_LEVEL_1 | \
                                       UART_DMAMODE |         \
                                       UART_FIFO_MODE );
    
        /* Wait for return from callback */     
        while(0 == flag);
        flag = 0;
        
        /* Transmit Data for Entered value */
        UartTransmitData(EDMA3_CHA_UART2_TX, EDMA3_CHA_UART2_TX, 
                         buffer, RX_BUFFER_SIZE);
    
        /* Enabling UART in DMA Mode*/
        UARTDMAEnable(SOC_UART_2_REGS, UART_RX_TRIG_LEVEL_1 |  \
                                       UART_DMAMODE |           \
                                       UART_FIFO_MODE );
    
        /* Wait for return from callback */
        while(0 == flag); 
        flag = 0;
    
        /* Free EDMA3 Channels for TX and RX */
        EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
                         EDMA3_CHA_UART2_TX, EDMA3_TRIG_MODE_EVENT, 
                         EDMA3_CHA_UART2_TX, EVT_QUEUE_NUM);
    
        EDMA3FreeChannel(SOC_EDMA30CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
                         EDMA3_CHA_UART2_RX, EDMA3_TRIG_MODE_EVENT, 
                         EDMA3_CHA_UART2_RX, EVT_QUEUE_NUM);
        
        while(1);
    
    }
    
    /*
    ** This function is used to set the PaRAM entries in EDMA3 for the Transmit Channel
    ** of UART. EDMA3 Enable Transfer is also called within this API.
    */
    
    static void UartTransmitData(unsigned int tccNum, unsigned int chNum,
                                 volatile char *buffer, unsigned int buffLength)
    {
        EDMA3CCPaRAMEntry paramSet;
    
        /* Fill the PaRAM Set with transfer specific information */
        paramSet.srcAddr = (unsigned int) buffer;
        paramSet.destAddr = UART_RBR_THR_REG;
        paramSet.aCnt = MAX_ACNT;
        paramSet.bCnt = (unsigned short) buffLength;
        paramSet.cCnt = MAX_CCNT;
    
        /* The src index should increment for every byte being transferred. */
        paramSet.srcBIdx = (short) 1u;
    
        /* The dst index should not be increment since it is a h/w register*/
        paramSet.destBIdx = (short) 0u;
      
        /* A sync Transfer Mode */
        paramSet.srcCIdx = (short) 0u;
        paramSet.destCIdx = (short) 0u;
        paramSet.linkAddr = (unsigned short)0xFFFFu;
        paramSet.bCntReload = (unsigned short)0u;
        paramSet.opt = 0x00000000u;
        paramSet.opt |= (EDMA3CC_OPT_DAM );
        paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
        paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
    
        /* Now write the PaRAM Set */
        EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, &paramSet);
    
        /* Enable EDMA Transfer */
        EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);
    }
    
    /*
    ** This function is used to set the PARAM SET of EDMA3 for the Receive Channel
    ** of UART. EDMA3 Enable Transfer is also called within this API.
    */
    
    static void UartReceiveData(unsigned int tccNum, unsigned int chNum,
                                volatile char *buffer)
    {
        EDMA3CCPaRAMEntry paramSet;
    
        /* Fill the PaRAM Set with transfer specific information */
        paramSet.srcAddr = UART_RBR_THR_REG;
        paramSet.destAddr = (unsigned int) buffer;
        paramSet.aCnt = MAX_ACNT;
        paramSet.bCnt = RX_BUFFER_SIZE;
        paramSet.cCnt = MAX_CCNT;
    
        /* The src index should not be increment since it is a h/w register*/
        paramSet.srcBIdx = 0;
        /* The dest index should incremented for every byte */
        paramSet.destBIdx = 1;
    
        /* A sync Transfer Mode */
        paramSet.srcCIdx = 0;
        paramSet.destCIdx = 0;
        paramSet.linkAddr = (unsigned short)0xFFFFu;
        paramSet.bCntReload = 0;
        paramSet.opt = 0x00000000u;    
        paramSet.opt |= ((EDMA3CC_OPT_SAM) << EDMA3CC_OPT_SAM_SHIFT); 
        paramSet.opt |= ((tccNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
        paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
    
        /* Now write the PaRAM Set */
        EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, chNum, &paramSet);
    
        /* Enable EDMA Transfer */
        EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum, EDMA3_TRIG_MODE_EVENT);
    }
    
    /* Function used to Initialize EDMA3 */
    static void EDMA3Initialize(void)
    {
        /* Enabling the PSC for EDMA3CC_0.*/ 
        PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON,
    		     PSC_MDCTL_NEXT_ENABLE);
    
        /* Enabling the PSC for EDMA3TC_0.*/
        PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON,
    		     PSC_MDCTL_NEXT_ENABLE);
    
        /* Initialization of EDMA3 */    
        EDMA3Init(SOC_EDMA30CC_0_REGS, EVT_QUEUE_NUM);
       
        /*
        ** Enable AINTC to handle interuppts. Also enable IRQ interuppt in 
        ** ARM processor.
        */
        SetupInt();
    
        /* Register EDMA3 Interrupts */
        ConfigureIntEDMA3();
    }
    
    /* Function used to Setup ARM Interuppt Controller */
    static void SetupInt(void)
    {
    #ifdef _TMS320C6X
    	// Initialize the DSP Interrupt controller
    	IntDSPINTCInit();
    
    	// Enable DSP interrupts globally
    	IntGlobalEnable();
    #else
        /*Initialize the ARM Interrupt Controller(AINTC). */
        IntAINTCInit();
    
        /* Enable IRQ in CPSR.*/     
        IntMasterIRQEnable();
    
        /* Enable the interrupts in GER of AINTC.*/
        IntGlobalEnable();
    
        /* Enable the interrupts in HIER of AINTC.*/
        IntIRQEnable();
    #endif
    }
    
    /* EDMA3 Completion Handler */
    static void edma3ComplHandler(unsigned int baseAdd, unsigned int regionNum)
    {
        volatile unsigned int pendingIrqs;
        volatile unsigned int isIPR = 0;
    
        unsigned int indexl;
        unsigned int Cnt = 0;
        indexl = 1;
        
    #ifdef _TMS320C6X
        IntEventClear(SYS_INT_EDMA3_0_CC0_INT1);
    #else
        IntSystemStatusClear(SYS_INT_CCINT0);
    #endif
        isIPR = HWREG(baseAdd + EDMA3CC_S_IPR(regionNum));
        if(isIPR)
        {
            while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0u))
            {
                indexl = 0u;
                pendingIrqs = HWREG(baseAdd + EDMA3CC_S_IPR(regionNum));
                while (pendingIrqs)
                {
                    if((pendingIrqs & 1u) == TRUE)
                    {
                        /**
                        * If the user has not given any callback function
                        * while requesting the TCC, its TCC specific bit
                        * in the IPR register will NOT be cleared.
                        */
                        /* here write to ICR to clear the corresponding IPR bits */
                        HWREG(baseAdd + EDMA3CC_S_ICR(regionNum)) = (1u << indexl);
    
                        (*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
                    }
                    ++indexl;
                    pendingIrqs >>= 1u;
                }
                Cnt++;
            }
        }
    }
    
    static void Edma3ComplHandlerIsr(void)
    {
    #ifdef _TMS320C6X
    	// Invoke Completion Handler ISR
    	edma3ComplHandler(SOC_EDMA30CC_0_REGS, 1);
    #else
        /* Invoke Completion Handler ISR */
        edma3ComplHandler(SOC_EDMA30CC_0_REGS, 0);
    #endif
    }
    
    /* EDMA3 Error Handler */
    static void edma3CCErrHandler(unsigned int baseAdd)
    {
        volatile unsigned int pendingIrqs = 0;
        unsigned int regionNum = 0;
        unsigned int evtqueNum = 0;  
        unsigned int index = 1;
        unsigned int Cnt = 0;
        
    #ifdef _TMS320C6X
        IntEventClear(SYS_INT_EDMA3_0_CC0_ERRINT);
    #else
        IntSystemStatusClear(SYS_INT_CCERRINT);
    #endif
    
        if((HWREG(baseAdd + EDMA3CC_EMR) != 0 ) || \
           (HWREG(baseAdd + EDMA3CC_QEMR) != 0) || \
           (HWREG(baseAdd + EDMA3CC_CCERR) != 0))
        {
            /* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time, breaks 
               when no pending interrupt is found */
            while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0u))
            {
                index = 0u;
                pendingIrqs = HWREG(baseAdd + EDMA3CC_EMR);
                while (pendingIrqs)
                {
                    /*Process all the pending interrupts*/
                    if((pendingIrqs & 1u)==TRUE)
                    {
                        /* Write to EMCR to clear the corresponding EMR bits.*/
                        HWREG(baseAdd + EDMA3CC_EMCR) = (1u<<index);
                        /*Clear any SER*/
                        HWREG(baseAdd + EDMA3CC_S_SECR(regionNum)) = (1u<<index);
                    }
                    ++index;
                    pendingIrqs >>= 1u;
                }
                index = 0u;
                pendingIrqs = HWREG(baseAdd + EDMA3CC_QEMR);
                while (pendingIrqs)
                {
                    /*Process all the pending interrupts*/
                    if((pendingIrqs & 1u)==TRUE)
                    {
                        /* Here write to QEMCR to clear the corresponding QEMR bits*/
                        HWREG(baseAdd + EDMA3CC_QEMCR) = (1u<<index);
                        /*Clear any QSER*/
                        HWREG(baseAdd + EDMA3CC_S_QSECR(0)) = (1u<<index);
                    }
                    ++index;
                    pendingIrqs >>= 1u;
                }
                index = 0u;
                pendingIrqs = HWREG(baseAdd + EDMA3CC_CCERR);
        if (pendingIrqs != 0u)
        {
            /* Process all the pending CC error interrupts. */
            /* Queue threshold error for different event queues.*/
            for (evtqueNum = 0u; evtqueNum < EDMA3_0_NUM_EVTQUE; evtqueNum++)
            {
                if((pendingIrqs & (1u << evtqueNum)) != 0u)
                {
                    /* Clear the error interrupt. */
                    HWREG(baseAdd + EDMA3CC_CCERRCLR) = (1u << evtqueNum);
                }
             }
    
             /* Transfer completion code error. */
             if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0u)
             {
                 HWREG(baseAdd + EDMA3CC_CCERRCLR) = \
                      (0x01u << EDMA3CC_CCERR_TCCERR_SHIFT);
             }
             ++index;
        }
        Cnt++;
            }
        }
    }
    
    static void Edma3CCErrHandlerIsr()
    {
        /* Invoke CC Error Handler ISR */
        edma3CCErrHandler(SOC_EDMA30CC_0_REGS);
    }
    
    /* Function to register EDMA3 Interuppts */
    static void ConfigureIntEDMA3(void)
    {
        /* Register Interrupts Here */
    
    #ifdef _TMS320C6X
    	IntRegister(C674X_MASK_INT4, Edma3ComplHandlerIsr);
    	IntRegister(C674X_MASK_INT5, Edma3CCErrHandlerIsr);
    
    	IntEventMap(C674X_MASK_INT4, SYS_INT_EDMA3_0_CC0_INT1);
    	IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_ERRINT);
    
    	IntEnable(C674X_MASK_INT4);
    	IntEnable(C674X_MASK_INT5);
    #else
        IntRegister(SYS_INT_CCINT0, Edma3ComplHandlerIsr);
    
        IntChannelSet(SYS_INT_CCINT0, 2);
    
        IntSystemEnable(SYS_INT_CCINT0);
    
        IntRegister(SYS_INT_CCERRINT, Edma3CCErrHandlerIsr);
    
        IntChannelSet(SYS_INT_CCERRINT, 2);
    
        IntSystemEnable(SYS_INT_CCERRINT);
    #endif
    }
    
    
    /*
    ** This function is used as a callback from EDMA3 Completion Handler. 
    ** UART in DMA Mode is Disabled over here.
    */
    static void callback(unsigned int tccNum, unsigned int status)
    {
        UARTDMADisable(SOC_UART_2_REGS, (UART_RX_TRIG_LEVEL_1 | UART_FIFO_MODE));
        flag = 1;
    }
    
    /********************************* End of file ******************************/
    

  • Thanks for your response. I have developed my own software package (based on TRM and StarterWare) because of some reasons. But, I tried to mention registers name and other details in the first post. Sorry if that was not clear.
    Those threads are useful, but those are about using EDMA+UART, While I want to receive an unknown length data by RX-Timeout interrupt (EDMA+UART+RX-Timeout interrupt).
    I saw the BIOSPSP code of this device previously, but I didn't find any modes that use UART interrupt (RX-Timeout or others) with EDMA at the same time (Available modes in BIOSPSP are: Uart_OpMode_POLLED, Uart_OpMode_INTERRUPT => that does not use EDMA, and Uart_OpMode_DMAINTERRUPT that does not use UART-Interrupts and using for receive a fixed data length).

  • Hello,

    I'm not sure why a modem status interrupt would be occurring in that case. Have you tried disabling this interrupt?

    Is DMAMODE1 set in the FCR?

    Would you be able to provide us a test case so that we can reproduce on our end and take a closer look? 

  • Hamid,

    I'm going to close this thread and mark it as resolved for now. If you have any updates feel free to post a reply here to re-open the thread or create a new thread by pressing the "+ Ask a related question" button at the top if this thread has locked due to time.

    Regards,
    Sahin