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66AK2H14: Simulataneously accessing high-speed links

joe lindula
Mastermind 6930 points
Part Number: 66AK2H14
Other Parts Discussed in Thread: 66AK2E05

Hello, I was wondering it is possible for one DSP core to access PCIe channel 0 and another DSP core to access PCIe channel 1 at the same time? I wondering how the sharing of the high-speed interfaces is done within the device.

Thank you,

Joe 

  • 0
    Guru 13202 points

    Hello!

    If you think about PIO request, that is memory reads or writes to PCIe address window, this should not be done by multiple cores without mutual exclusion. It could look like Core0 makes power on setup, and all other cores acquire handles to peripheral, and make their accesses with help of some mutex. 

    However, this scenario is not what high speed really is. One may get some pretty performance numbers using DMA. If that is EDMA of your chip, one may program individual transfers to move data to/from cores' L2 memories, or other memory buffer. EDMA transfers normally run to completion, but if you setup chaining, there could multiple composite transfers serving multiple consumers with respective priorities.

  • 0
    TI__Guru**** 161600 points

    Hi Joe,

    In general you should be able to do this using DSPBIOS handles (semaphore locks, ipc and so on).

    Looping the design team to confirm/elaborate on this.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Mastermind 6930 points

    Yordan,

    HI, thanks for responding to my post. Is the DSPBIOS an RTOS? We were hoping to do Baremetal.

    Thanks,

    Joe

  • 0 in reply to joe lindula
    TI__Guru* 95265 points

    Hi,

    For 66AK2H14 device, there is ONLY 1 PCIE controller, but there are 2 PCIE Serdes lanes. You can configure the controller to use either the Serdes 0 only, or both Serdes 0 and Serdes 1. Each PCIE Serdes lane supports PCIE GEN1 or GEN2 speed.

    There is no such usage case that core 0 accesses the PCIE Serdes lane 0 and core 1 accesses PCIE serdes lane 1, because there is only 1 PCIE controller in this device.

    If you are looking for such a feature, you may consider devices such as 66AK2E05/02, it has two PCIE controllers and each controller has two PCIE Serdes lanes. 

    Regards, Eric 

  • 0 in reply to lding
    Mastermind 6930 points

    Eric,

    Hello, thank you for responding to my message. Is it possible for DSP 0 access SRIO Channel 1 and DSP 1 access SRIO Channel 2 simultaneously? How about the same for SGMII? Or, the 10GigE, DSP 1 accessing 10GigE channel 0 and DSP 2 accessing channel 1 simultaneously? I ask because my co-worker is not seeing the benefits of a multi-core system if in the end there is bus contention over the high-speed links.

    Please let me know if you have any comments.

    Thanks,

    Joe

  • 0 in reply to joe lindula
    TI__Guru* 95265 points

    Hi,

    For PCIE, if you look at the PCIE User guide: 

    The PCI Express module does not support the following features:
    • No support for using ×2 link as two ×1 links

    It is clear.

    For SRIO, it has only controller but it has 4 lanes. From SRIO user guide:

    • 4X Serial RapidIO with auto-negotiation to
    – 1X port, optional operation for (4) 1X ports
    – 2X port, optional operation for (2) 2X ports
    – 2X port and 1X port operation, optional operation for (1) 2X port and (2) 1X ports
    – 4x port, operation for (1) 4x port

     Yes, you can group separate Serdes lanes to certain ports. At maximum, you can have four device connected (to 4 ports) and each with 1x lane. Yes, you can use one DSP core to control a port (this port may have 1 lanes/ 2 lanes/ or 4 lanes).

    For SGMII, there are 4 controllers and in total 4 Serdes lanes. Each controller has 1 serdes lane. You can use different DSP core to control one SGMII port.

    We have PCIE, SRIO and SGMII examples in RTOS processor SDK.

    For XGE, there are 2 instances and 2 Serdes lanes, similar to SGMII, each controller has one lane. In theory you can have one DSP core control one XGE port. But we don't have XGE driver in RTOS. The XGE is only supported by Linux driver and there are 4 A15 cores in SMP mode to access both XGE 0 and 1.

    Regards, Eric