Hi,
We encountered a strange DDR2 hardware problem on our DM6437 board.
Configuration: L1D and L1P are used as cache. L2RAM is used as SRAM. We boot the board through UART0.
Source code of the problem.
volatile int * addr = (volatile int*) 0x80000000;
int tmp;
*addr = 0x5555aaaa;
tmp = *addr;
Surprisingly, tmp is not equal to '0x5555aaaa', as would expect.
When probing the waveform on DDR2 DQS and DQ[0-15] pins, we did see the waveform of write sequence on DQS and DQ[0-15], but we did not see any waveform of read sequence on DQS and DQ[0-15] pins caused by statement (tmp = *addr).
We initially thought it could be caused by L1D cache. So we disabled L1D cache, the results were still the same, no waveform of read sequence on DQS and DQ[0-15] pins. Then we lowered the DDR2 frequency, it did not help either.
For comparison, we tested the same program on DM6437 EVM board, and probed the waveforms. We are able to see both waveforms of write sequence by (*addr = 0x5555aaaa) statement, and read sequence by (tmp =*addr) statement.
Therefore, our suspect is that the DDR2 controller on our DM6437 chip does not work properly.
Following is our configuration of DDR2. Could you help to check if there is anything wrong? (We checked many times and could not find any error.)
Int16 DM6437_DDR_init( Uint32 freq )
/* Note: in our board, we set freq=162MHz, uses Micron MT47H32M16HR-3 chip. */
{
volatile Uint32 dummy_read;
volatile Uint32 pch_nch;
Uint32 refresh_rate;
EVMDM6437_PSC_changeState( 13, PSC_ENABLE );
DDR_DDRPHYCR = 0 // DDR PHY Control Register
| ( 0x5000<<16) // Magic Number: 5000h for upper
| ( 0x190 << 6 ) // Magic number: 190h for lower
| ( 0 << 5 ) // DLL release
| ( 0 << 4 ) // DLL powered up
| ( 6 << 0 ); // Read latency ( CAS + 1 ) // We use -3 speed DDR2, CAS is 5
DDR_SDBCR |= 0x00800000; // SDBCR boot unlock
DDR_SDBCR = 0 // DDR Bank Config
| ( 0 << 23 ) // Boot unlock = No
| ( 2 << 19 ) // Reserved = ( 2 )
| ( 0 << 18 ) // Drive Strength= normal driver for RRCamera
| ( 3 << 16 ) // Reserved = ( 3 )
| ( 1 << 15 ) // Modify SDTIMR & SDTIMR2 = Yes
| ( 1 << 14 ) // Bus width = 16-bit -- RRCamera uses 16bits only
| ( 5 << 9 ) // CAS latency = 5 // We use -3 speed DDR2, CAS is 5
| ( 2 << 4 ) // Bank Setup = 4 banks
| ( 2 << 0 ); // Page Size = 1024-word / 10 column bits
// DDR2 chip uses Micron MT47H32M16HR-3 chip.
// DDR2 clock is 162MHz or 6.17ns
DDR_SDTIMR = 0 // DDR Timing Register
| ( 11 << 25 ) // tRFC = ( 75 ns / 6.17 ns ) - 1
| ( 1 << 22 ) // tRP = ( 15 ns / 6.17 ns ) - 1
| ( 1 << 19 ) // tRCD = ( 15 ns / 6.17 ns ) - 1
| ( 1 << 16 ) // tWR = ( 15 ns / 6.17 ns ) - 1
| ( 6 << 11 ) // tRAS = ( 45 ns / 6.17 ns ) - 1
| ( 8 << 6 ) // tRC = ( 60 ns / 6.17 ns ) - 1
| ( 1 << 3 ) // tRRD = ( (4*10ns + 2*6.17ns) / 4*6.17ns ) - 1
| ( 0 << 0 ); // tWTR = ( 7.5 ns / 6.17 ns ) - 1
DDR_SDTIMR2 = 0 // DDR Timing Register
| ( 12 << 16 ) // tXSNR= ( 85 ns / 6.17 ns ) - 1
| ( 199 << 8 ) // tXSRD= ( 200 - 1 ) cycles
| ( 0 << 5 ) // tRTP = ( 7.5 ns / 6.17 ns ) - 1
| ( 2 << 0 ); // tCKE = ( 3 - 1 ) cycles
DDR_SDBCR &= ~0x00008000; // SDTIMR & SDTIMR2 cannot be modified 0x01936A22
refresh_rate = ( freq * 78 ) / 10;
DDR_SDRCR = 0
| ( 0 << 31 ) // Exits self-refresh
| ( 0 << 30 ) // Disable MCLK stopping
| refresh_rate; // Refresh Control = 7.8 usec * freq
dummy_read = *( volatile Uint32* )DDR_BASE;
/*
* Step 5 - Soft Reset ( SYNCRESET followed by ENABLE ) of DDR2 PHY
*/
EVMDM6437_PSC_changeState( 13, PSC_SYNCRESET );
EVMDM6437_PSC_changeState( 13, PSC_ENABLE );
/*
* Step 6 - Enable VTP calibration
* Step 7 - Wait for VTP calibration ( 33 VTP cycles )
*/
DDR_VTPIOCR = 0x201F;
DDR_VTPIOCR = 0xA01F;
_wait( 1500 );
/*
* Step 8 - Enable access to DDR VTP reg
* Step 9 - Reat P & N channels
* Step 10 - Set VTP fields PCH & NCH
*/
DDR_DDRVTPER = 1;
pch_nch = DDR_DDRVTPR & 0x3FF;
DDR_VTPIOCR = 0xA000 | pch_nch;
/*
* Step 11 - Disable VTP calibaration
* - Disable access to DDR VTP register
*/
DDR_VTPIOCR &= ~0x2000;
DDR_DDRVTPER = 0;
return 0;
}
