Hello,
I am trying to initialize the DDR2 for our board. I have been using the LogicPD Gel file as a template because that is what this post says to do:
http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/115/p/60850/218071.aspx#218071 the problem is I cannot get anything on the DDR2. i get data verification errors and when I open up the memory map i see all 0's even if i manually write 0xAA to any location. Here is my Gel init for PLL1 and DDR2. the DDR2 part number we are using is MT47H32M16HR-3. I have been recalculating timings and ajusting clocks and i can't seem to get this to work....
/******************************************************************************/ /* Setup_PLL1() */ /* */ /* CLKIN = 24.576MHz cyrstal. */ /******************************************************************************/ Setup_PLL1( ) { int PoweredDown = ((PLL1_PLLCTL & 0x00000002) >> 1); int div1; int div2; int div3; int pll1_freq; GEL_TextOut("\n ***** PLL1 *****\n" ); /* Step 1 - Set clock mode */ if( PoweredDown == 1 ) { PLL1_PLLCTL = PLL1_PLLCTL & 0xFFFFFEFF; /* Select Onchip Oscillator */ } /* Step 2 - Set PLL to bypass and wait for PLL to stabilize */ PLL1_PLLCTL = PLL1_PLLCTL & 0xFFFFFFDF; /* clear PLLENSRC so PLLEN can take effect */ PLL1_PLLCTL = PLL1_PLLCTL & 0xFFFFFDFF; /* set clock source to be OSCIN */ PLL1_PLLCTL = PLL1_PLLCTL & 0xFFFFFFFE; /* Switch to bypass mode */ CPUCycleDelay( 500 ); /* Wait at least 4 CLKIN cycles(0.16uS) (150 = 6.1uS) */ /* Step 3 - Reset PLL */ PLL1_PLLCTL = PLL1_PLLCTL & 0xFFFFFFF7; /* Start Reset of PLL1 */ /* Step 4 - Powerup PLL */ if( PoweredDown == 1 ) { PLL1_PLLCTL = PLL1_PLLCTL & 0xFFFFFFFD; /* Power up PLL */ } /* Step 5 - Load PLL multiplier */ PLL1_PLLM = 0x00000004; /* Set for x6 (PLLM + 1) */ /* Step 6 - Load PLL dividers(1:DSP, 2:UART0, LCDC, DDR2, SPI0 3:EMIFA ) */ while( (PLL1_PLLSTAT & 1) != 0 ); /* Wait for any previous GO operations to finish */ PLL1_PLLDIV1 = 0x00008000; /* Divide-by-1 */ PLL1_PLLDIV2 = 0x00008001; /* Divide-by-2 */ PLL1_PLLDIV3 = 0x00008002; /* Divide-by-3 */ PLL1_PLLCMD = PLL1_PLLCMD | 0x00000001; /* Set new divider values and phase alignment */ while( (PLL1_PLLSTAT & 1) != 0 ); /* Wait for GO operation to finish */ /* Step 7 - Release from reset */ PLL1_PLLCTL = PLL1_PLLCTL | 0x00000008; /* Take PLL1 out of RESET /* Step 8 - Wait for PLL to re-lock Step 9 - Switch from BYPASS mode to PLL mode */ CPUCycleDelay( 65536 ); /* Wait at least 535 cycles (PLL Lock Time) 2000/sqrt(PLLM) = 535 OSCIN CLK cycles */ PLL1_PLLCTL = PLL1_PLLCTL | 0x00000001; /* Switch to EN PLL mode */ pll1_freq = 24.576 * ((PLL1_PLLM & 0x0000001F) + 1); div1 = PLL1_PLLDIV1 & 0x0000001F; div2 = PLL1_PLLDIV2 & 0x0000001F; div3 = PLL1_PLLDIV3 & 0x0000001F; GEL_TextOut( "DDR2 = %d MHz \n",,,,, (pll1_freq / ( div1 + 1 )) ); GEL_TextOut( "SPI1 = %d MHz .... \n",,,,, (pll1_freq / ( div2 + 1 )) ); GEL_TextOut( "SYSCLK3 Phy = %d MHz .... \n",,,,, (pll1_freq / ( div3 + 1 )) ); GEL_TextOut( "[Done]\n" ); }
/******************************************************************************/ /* Setup_DDR2() */ /* */ /* DDR2 = 32M x 16 @ 147.46MHz */ /******************************************************************************/ Setup_DDR2( ) { int dummy_read; int pch_nch; GEL_TextOut( "Setup DDR2 Memory Controller... "); /* Step 1 - Setup PLL2 Step 2 - Enable DDR2 PHY */ //shoudl already be enabled.... psc_change_state1( LPSC_DDR2, LPSC_STATE_ENABLE ); /* Step 3 - Enable VTP calibration Step 4 - Wait for VTP calibration */ if((VTPIO_CTL & 0x00000040)) { DDR_VTPIOCR |= (0x00004000); // Set IOPWRDN bit to enable input buffer powerdown enable mode DDR_VTPIOCR &= ~(0x00000040); // Clear POWERDN bit (enable VTP) // Pulse (low) CLRZ to initiate VTP IO Calibration DDR_VTPIOCR |= (0x00002000); // Set CLRZ bit DDR_VTPIOCR &= ~(0x00002000); // Clear CLRZ bit (CLRZ should be low for at least 2ns) CPUCycleDelay( 50 ); DDR_VTPIOCR |= 0x00002000; // Set CLRZ bit while((DDR_VTPIOCR & 0x00008000) != 0x00008000); //wait for ready (bit 15) DDR_VTPIOCR |= 0x00000080; // Set LOCK bit for static mode DDR_VTPIOCR |= 0x00000100; // Set PWRSAVE bit to save power DDR_VTPIOCR |= 0x00000040; // Set POWERDN bit to power down VTP module } /* Step 5 alter bus priority register */ DDR_PBBPR = 0x00000015; // Enable the Peripheral Bus Burst Priority Register /* Step 6 - DDR2 Initialization */ DDR_SDCR |= 0x00800000; // Set BOOTUNLOCK DDR_DDRPHYCR = 0x000000C3; // DLL powered up and NOT in reset, ReadLatency=3 DDR_SDCR = 0x0010C622; // Unlock Timer Regs, 16-bit bus, CAS=3, 4 banks, 1024-word page //for 147.46MHz //DDR_SDTIMR = 0x1E922A09; // DDR Timing ( set for 129.024MHz ) //DDR_SDTIMR2 = 0x3C10C722; // DDR Timing ( set for 129.024MHz ) //for 122.73MHz DDR_SDTIMR = 0x1A9229C9; // DDR Timing ( set for 129.024MHz ) DDR_SDTIMR2 = 0x3C0EC722; // DDR Timing ( set for 129.024MHz ) DDR_SDCR = DDR_SDCR & 0xFFFF7FFF; // Lock Timer Regs DDR_SDCR2 = 0x00000000; // IBANK_POS set to 0 so this register does not apply DDR_SDRCR = 0xC000047E; // Refresh Control [ 7.8 usec * 147.46MHz ] /* Step 7 - Soft Reset ( SYNCRESET followed by ENABLE ) of DDR2 PHY */ psc_change_state1( LPSC_DDR2, LPSC_STATE_SYNCRESET ); psc_change_state1( LPSC_DDR2, LPSC_STATE_ENABLE ); DDR_SDRCR &= ~0xC0000000; // disable self-refresh GEL_TextOut( "[Done]\n" ); }
