Hi,
We are looking for pinmux configurations for DCAN2_TX, but we couldn't find on the file (csl/soc/tda3xx/hw_ctrl_core_pad_io.h). Right now we are trying to enable GPMC_WAIT1 signal, Could you please provide the proper configuration for GPMC_WAIT1 signal on DCAN2_TX Pads.
E.g DCAN2_TX/VIN2A_DE0/VIN2A_HYSNC0/SPI1_CS2/UART3_RXD/QSPI1_CS1/GMPC_WAIT1/VIN1B_HSYNC1 35
We are looking proper macro definition for the below configuration
{CTRL_CORE_PAD_IO_DCAN2_TX,
CTRL_CORE_PAD_IO_DCAN2_TX_MUXMODE_GPMC_WAIT1_0,
PULLUDENABLE_DISABLE, PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE,
0xff, 0xff},
We noticed some changes in qspi pinumx configuration, The below configuration is taken from the file (csl/soc/tda3xx/hw_ctrl_core_pad_io.h).
{CTRL_CORE_PAD_IO_GPMC_CS5,
CTRL_CORE_PAD_IO_GPMC_CS5_MUXMODE_QSPI1_D0_1,
PULLUDENABLE_ENABLE, PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE,
0xff, 0xff},
{CTRL_CORE_PAD_IO_GPMC_CS4,
CTRL_CORE_PAD_IO_GPMC_CS4_MUXMODE_QSPI1_D1_1,
PULLUDENABLE_ENABLE, PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE,
0xff, 0xff},
The above qspi configuration seems to be little bit confusing for us. I think we have to modify this configuration like below,
{CTRL_CORE_PAD_IO_GPMC_CS4,
CTRL_CORE_PAD_IO_GPMC_CS4_MUXMODE_QSPI1_D0_1,
PULLUDENABLE_ENABLE, PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE,
0xff, 0xff},
{CTRL_CORE_PAD_IO_GPMC_CS5,
CTRL_CORE_PAD_IO_GPMC_CS5_MUXMODE_QSPI1_D1_1,
PULLUDENABLE_ENABLE, PULLTYPESELECT_PULL_UP, INPUTENABLE_ENABLE,
0xff, 0xff},
Regards
Prakash
