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NVIC_EnableIRQ : enables only one interrupt at a time?

Haio Maio1
Prodigy 20 points

Looking at the one of the implementations of NVIC_EnableIRQ, Im wondering how the ISER works

static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}

Calling the above two consequitve times with a different IRQn, will erase the enable of the previous interrupt. Does it mean I can enable one interrupt at a time?

NVIC_EnableIRQ(8);   // enables IRQ8

NVIC_EnableIRQ(7);   // enables IRQ7 but disables IRQ8 ?!?

Correct, or do I miss something? Am I enabling two IRQs at a time? If yes, how is it possible, if ISER[0] would contain only the last assignment....

Further, can I set an IER of a peripheral device without enabling its interrupt ?!?

For example, can I set the IER below

LPC_UART3->IER = 0x00000005UL;            // Enable UART3 interrupt RBR ans RLS

without calling before it

NVIC_EnableIRQ(UART3_IRQn);

?

Where do I need to use 

NVIC_EnableIRQ

and/or where do I need to set the corresponding peripheral

  

IER

?

Thanks in advance !

  • 0
    TI__Guru**** 393215 points

    What processor is this? What software? Which version?

  • 0
    Guru 99475 points

    The ISER works as described in the Cortex-M4 Generic User Guide (DUI0553A) Sec 4.2.2: Writing a 1 to a bit enables that IRQ, writing a 0 has no effect. (That's why it's the Set Enable, not the Enable register.) The other Cortex-M ISER-s work the same.

    NVIC_EnableIRQ won't enable more than one IRQ since an IRQn is a small integer, so there's no way to pass two values in.

    In most cases you need to request a peripheral to generate an IRQ (UART->IER in your example) as well as request the NVIC to accept it (NVIC->ISER).

  • 0 in reply to Bruce McKenney
    Prodigy 20 points

    Bruce McKenney47378 said:

    In most cases you need to request a peripheral to generate an IRQ (UART->IER in your example) as well as request the NVIC to accept it (NVIC->ISER).

    According to the spec, the IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts.

    This doesn't mean, I request an IRQ to be generated, neither it means I need the ISER to request it. This means, I am not able to find anywhere a passage in the specification, that both ISER and IER are related and co-dependent.

    It seems they are independent by design.

    Is it meant to be like this?

  • 0 in reply to Haio Maio1
    Guru 99475 points

    > It seems they are independent by design.

    Yes, that is correct.