How to enable RGMII1 for ethernet?

user6000372

Hi Sir,

Our project is based DRA78x, the SDK is ti-processor-sdk-rtos-automotive-dra7xx-evm-04.03.00.05.

We use RGMII1 to connect ethernet,the pin mux is as below,I find nimu is only for RGMII0,could you give any suggestions?

over 5 years ago

0 Peter Li79 over 5 years ago

TI__Expert 8940 points

Hi,

The Ethernet works with RGMII0 (on TDA3 EVM).

Customer's hardware is using RGMII1 due to the conflict of SD/MMC and RGMII0 (compared with TI TDA3 EVM).

Please kindly guide us on how to make it work (RGMII1) on customer's hardware.

Many thanks.

0 Danny Jochelson over 5 years ago in reply to Peter Li79

TI__Intellectual 870 points

Hi,

Once the desired pinmux settings for RMGII1 have been determined by the pinmux tool (i.e. your screenshot indicates you are using the pinmux tool), the pinmux settings will need to be changed in the PinmuxRgmiiConfig() function within the <PDK>/packages/ti/board/src/evmDRA78x/evmDRA78x.c to instead set up the pin muxing for RGMII1.

In addition, the following change should be done in the NIMU example found here: <PDK>/packages/ti/transport/ndk/nimu/example/src/main_evmDRA7xx.c

cfg.port[0].phy_addr = EMAC_CPSW_PORT0_PHY_ADDR_EVM;

cfg.port[0].phy_addr = EMAC_CPSW_PORT1_PHY_ADDR_EVM;

After making these changes, the PDK should be rebuilt, following by a rebuild of the NIMU example. This should then allow you to utilize the NIMU example using RGMII1.

Danny

0 user6000372 over 5 years ago in reply to Danny Jochelson

Intellectual 560 points

Hi Danny,

Many thanks for your reply.

I do as your suggestion,unfortunately rgmii1 can't work. I think we do some change about emac driver.

Best Regards,

He Weibing

0 Peter Li79 over 5 years ago in reply to user6000372

TI__Expert 8940 points

Hi, Weibing:

Would you please share more details? So TI can help you continue the debug.

Many thanks.

0 Anand Mahadevan SS over 5 years ago in reply to Peter Li79

TI__Expert 8165 points

Hi Weibing,

As far as the nimu driver is considered, passing the correct phy addr to the HwAttrs cfg in your application is one step, as Danny mentioned. Make sure that you follow what's done in the example and make the corresponding change in your app. If you use the macros like EMAC_CPSW_PORT1_PHY_ADDR_EVM, which I think are defined in the file, make sure they point to correct values. Do you know if DUAL_MAC_MODE is enabled? If yes, I believe there could be some issue when you switch the RGMII port.

Regards,
Anand

0 user6000372 over 5 years ago in reply to Peter Li79

Intellectual 560 points

The log shows phy can't be found.

#################### Log begins####################################################

Jumping to IPU1 CPU0 App
SetPhyMode:000021e1 Auto:1, FD10:64, HD10:32, FD100:256, HD100:128, FD1000:8192 LPBK:0

SetPhyMode:000021e1 Auto:1, FD10:64, HD10:32, FD100:256, HD100:128, FD1000:8192 LPBK:0

Network Added: If-1:192.168.1.4

netOpenHook

-->Proc create: 0

ENETPHY_FindingState: Timed Out looking for a Phy!

Proc create: 0 is ready

ENETPHY_FindingState: Timed Out looking for a Phy!

########################Log Ends##################################################

I have a questions:

Is RGMII0 port1? is RGMII1 port2?

when RGMII0 works,should port0(host) also work?

If it is, I think we should include the port2,that's to say we should change DRA78XX_EVM_NUM_PORTS from 1 to 2.

I have a try to enable dual mac,the same problem show,the phy0 can be found.phy1 can't be found.

Could you give me any suggestions?

Many thanks,

He Weibing

0 user6000372 over 5 years ago in reply to Anand Mahadevan SS

Intellectual 560 points

Hi Anand,

Thanks for your reply.

I also enable the macros DUAL_MAC_MODE,the same problem occurs,phy0 can be found, PHY1 can't be found.

Best Regards,

He Weibing

0 user6000372 over 5 years ago in reply to Anand Mahadevan SS

Intellectual 560 points

Hi Anand,

The phymask is 2,but the value of MDIO_ALIVE is 1.

I don't know the relation between RGMII1/RGMII2 and phy.

Could you give me any suggestions?

Many thanks,

He Weibing

0 Misael Lopez Cruz over 5 years ago in reply to user6000372

TI__Genius 9295 points

If MDIO_ALIVE hardware register is showing only 1 bit set, then only one PHY is being detected in the MDIO bus. This is regardless of your software masks, etc.

MDIO_ALIVE will have a bit set for each PHY detected on the bus. For instance, a value of 1 indicates that PHY with address 0 is detected (i.e. BMSR register can be read).

What are the addresses of the PHYs connected to each RGMII port? What's the address of the PHY that's not showing in MDIO_ALIVE? Check that the PHY is powered and out-of-reset.

0 user6000372 over 5 years ago in reply to Misael Lopez Cruz

Intellectual 560 points

Hi,

The Phy can be found,but we don't ping the phy from pc.

pc address:192.168.1.10

dra78x board:192.168.1.4

emac negotiated with phy to use FullDuplex 1000Mbs from the below log,but the value of register 0x48485200 is 0x30,it shows half-duplex and 100Mbps mode,it seems the regester doesn't match with log,

##################log################################################################

Jumping to IPU1 CPU0 App
SetPhyMode:000021e1 Auto:1, FD10:64, HD10:32, FD100:256, HD100:128, FD1000:8192 LPBK:0

Network Added: If-1:192.168.1.4

netOpenHook

-->Proc create: 0

ENETPHY_FindingState: PhyNum: 1

ENETPHY_DisablePhy(1)

Enable Phy to negotiate external connection

NWAY Advertising: FullDuplex-1000 FullDuplex-100 HalfDuplex-100 FullDuplex-10 HalfDuplex-10

Proc create: 0 is ready

Negotiated connection: FullDuplex 1000 Mbs

GotIP Address

#########################Log########################################################

Best Regards,

He Weibing

0 user6000372 over 5 years ago in reply to user6000372

Intellectual 560 points

Sorry for last comment.

"but the value of register 0x48485200 is 0x30" is wrong,the register is 0x48485288,its value is 0x30.

0 Danny Jochelson over 5 years ago in reply to user6000372

TI__Intellectual 870 points

Hi, He Weibing,

A common scenario where you are not able to ping from the PC to the target is incorrect pin muxing for the RGMII1. Can you confirm your pin muxing is correct?

Your log seems to indicate that the Phy is likely powered up correctly now. Can you share the values of the pin mux registers?

Danny

0 Peter Li79 over 5 years ago in reply to Danny Jochelson

TI__Expert 8940 points

Hi, Danny:

Here is the dump:

0x4A00 3408 CTRL_CORE_PAD_GPMC_BEN1 rgmii1_txd3 0x00000001
0x4A00 3434 CTRL_CORE_PAD_GPMC_WAIT0 rgmii1_rxd3 0x00040001
0x4A00 3438 CTRL_CORE_PAD_GPMC_AD0 rgmii1_rxd2 0x00040001
0x4A00 343C CTRL_CORE_PAD_GPMC_AD1 rgmii1_rxd1 0x00040001
0x4A00 3440 CTRL_CORE_PAD_GPMC_AD2 rgmii1_rxd0 0x00040001
0x4A00 346C CTRL_CORE_PAD_GPMC_AD13 rgmii1_rxc 0x00040001
0x4A00 3418 CTRL_CORE_PAD_GPMC_CS0 rgmii1_rxctl 0x00040001

0x4A00 340C CTRL_CORE_PAD_GPMC_ADVN_ALE rgmii1_txd2 0x00000001
0x4A00 3410 CTRL_CORE_PAD_GPMC_OEN_REN rgmii1_txd1 0x00000001
0x4A00 3414 CTRL_CORE_PAD_GPMC_WEN rgmii1_txd0 0x00000001
0x4A00 3400 CTRL_CORE_PAD_GPMC_CLK rgmii1_txc 0x00000001
0x4A00 3404 CTRL_CORE_PAD_GPMC_BEN0 rgmii1_txctl 0x00000001

I think the pinmux is correct.

0 Prasad Jondhale over 5 years ago in reply to user6000372

TI__Mastermind 27743 points

As discussed during debug call, we needed to do below changes for using RGMII1 along with setting PHY Address for port 1

#define EMAC_CPSW_PORT1_PHY_ADDR_EVM 1 /* set address here */

cfg.port[1].phy_addr = EMAC_CPSW_PORT1_PHY_ADDR_EVM;

#define DRA7XX_EVM_NUM_PORTS 2 /* Make this 2 to use RGMII1 */

Along with this we would need to set mdioModeFlags to one supported by PHY

Regards,

Prasad

0 user6000372 over 5 years ago in reply to user6000372

Intellectual 560 points

Peter Li and Prasad Jonhale help us to fix this issue,many thanks.

Best Regards,

He Weibing

Processors

Processors forum

How to enable RGMII1 for ethernet?