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CCS/AM5728: DSP eCAP interrupt issue

Sylvain PALMERI
Expert 1145 points
Part Number: AM5728

Tool/software: Code Composer Studio

Hello,

I have some troubles to get interrupts from input capture ECAP1. Below is part of the code I wrote:

1. Pinmux setting acording to my HW into the library:

void PinmuxECAP1Config()
{
    Uint32 regVal = 0U;

    regVal = 0U;
    CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D2_VIN2A_D2_WAKEUPENABLE, DISABLE);
    CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D2_VIN2A_D2_INPUTENABLE, ENABLE);
    CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D2_VIN2A_D2_PULLTYPESELECT, PULL_UP);
    CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D2_VIN2A_D2_PULLUDENABLE, ENABLE);
    CSL_FINST(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D2_VIN2A_D2_MODESELECT, MUX_MODE);
    CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D2_VIN2A_D2_DELAYMODE, 0U);
    CSL_FINS(regVal, CONTROL_CORE_PAD_IO_PAD_VIN2A_D2_VIN2A_D2_MUXMODE, 10U);
   ((CSL_padRegsOvly) CSL_MPU_CORE_PAD_IO_REGISTERS_REGS)->PAD_VIN2A_D2 = regVal;
}

2. activate the clock of the PWMSS1 module into the library:

    CSL_FINST(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_MODULEMODE, ENABLE);
        
    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_PWMSS1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER2_PRUSS1_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER2_PRUSS1_CLKCTRL_REG_IDLEST));

3.  ECAP1 interrupt setting in the application:

    /* XBar configuration */
    CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_32, CSL_XBAR_PWMSS1_IRQ_eCAP0INT);

    Intc_Init();
    Intc_IntEnable(0);

    /* Register ISR */
    Intc_IntRegister(APP_ECAP1_INT, (IntrFuncPtr) AppEcapIntrISR, 0);
    Intc_IntPrioritySet(APP_ECAP1_INT, 1, 0);

    Intc_SystemEnable(APP_ECAP1_INT);

4. ECAP1 module initialisation:

    /* enables clock for ECAP module */
    ECAPClockEnable(ECAP_BASE_ADDRESS);
    /* Disable all capture interrupts */
    ECAPIntDisable(ECAP_BASE_ADDRESS, ECAP_ECEINT_CEVT1 |
                                      ECAP_ECEINT_CEVT2 |
                                      ECAP_ECEINT_CEVT3 |
                                      ECAP_ECEINT_CEVT4 |
                                      ECAP_ECEINT_CTROVF |
                                      ECAP_ECEINT_CTR_PRD |
                                      ECAP_ECEINT_CTR_CMP);
    /* Clear all CAP interrupt flags */
    ECAPGlobalIntEnable(ECAP_BASE_ADDRESS);
    /* Disable CAP1-4 register loads at capture event time */
    ECAPCaptureLoadingDisable(ECAP_BASE_ADDRESS);
    /* Stop the counter */
    ECAPCounterControl(ECAP_BASE_ADDRESS, ECAP_COUNTER_STOP);

    /* Capture Events on Rising Edge */
    ECAPCapeEvtPolarityConfig(ECAP_BASE_ADDRESS, ECAP_CAPPOL_RE,            // Capture Event 1 polarity
                                                 ECAP_CAPPOL_RE,            // Capture Event 2 polarity
                                                 ECAP_CAPPOL_RE,            // Capture Event 3 polarity
                                                 ECAP_CAPPOL_RE);           // Capture Event 4 polarity
    /* Do not reset counter on Capture Event (absolute time stamp) */
    ECAPCaptureEvtCntrRstConfig(ECAP_BASE_ADDRESS, ECAP_CTRRST_ABS_MODE,    // Counter reset on Capture Event 1
                                                   ECAP_CTRRST_ABS_MODE,    // Counter reset on Capture Event 2
                                                   ECAP_CTRRST_ABS_MODE,    // Counter reset on Capture Event 3
                                                   ECAP_CTRRST_ABS_MODE);   // Counter reset on Capture Event 4
    /* Enable CAP1-4 register loads at capture event time */
    ECAPCaptureLoadingEnable(ECAP_BASE_ADDRESS);
    /* By-pass the prescaler */
    ECAPPrescaleConfig(ECAP_BASE_ADDRESS, ECAP_PRESCALE_DIV1);
    /* ECAP module operates in capture mode */
    ECAPOperatingModeSelect(ECAP_BASE_ADDRESS, ECAP_CAPTURE_MODE);
    /* Operate in continuous mode */
    ECAPContinousModeConfig(ECAP_BASE_ADDRESS);
    /* Disable sync-in option & sync-out signal */
    ECAPSyncInOutSelect(ECAP_BASE_ADDRESS, ECAP_SYNC_IN_DISABLE, ECAP_SYNC_OUT_DISABLE);
    /* TSCTR free-running */
    ECAPCounterControl(ECAP_BASE_ADDRESS, ECAP_COUNTER_FREE_RUNNING);

    /* Interrupt on Event 1 */
    ECAPIntEnable(ECAP_BASE_ADDRESS, ECAP_ECEINT_CEVT1);

The input is toggling with a TTL square signal but the ISR sub-routine never trigs... Do you have any suggestion to help to figure out the issue?

Thanks in advance,

Sylvain

  • 0
    TI__Genius 15920 points

    Hi Sylvain,

    Several of the ECAP registers (i.e. ECCTL1/2, ECEINT, etc.) are 16-bit wide registers.  Are you using 16-bit or 32-bit wide accesses to write to these registers?

    Please note that these registers require 16-bit wide accesses.  32-bit wide accesses will not work. You might also check the ECAP registers in CCS after your "ECAP1 module initialization" code to confirm that they contain the expected value.

    Regards,

    Melissa

  • 0 in reply to melissaw
    Expert 1145 points

    Hi Melissa,

    Thank you for your feedback.

    I checked if the register are well written and it's ok. The interrupt flag is set, but I still not go into the ISR. So I think that the problem is coming from the interrupt configuration routine:

    /* ======================================================================== */
    /*  ECAPIntConfig --                                                        */
    /* ======================================================================== */
    static void ECAPIntConfig(void)
    {
        /* XBar configuration */
        CSL_xbarIrqConfigure (CSL_XBAR_IRQ_CPU_ID_DSP1, CSL_XBAR_INST_DSP1_IRQ_32, CSL_XBAR_PWMSS1_IRQ_eCAP0INT);

        Intc_Init();
        Intc_IntEnable(0);

        /* Register ISR */
        Intc_IntRegister(APP_ECAP1_INT, (IntrFuncPtr) AppEcapIntrISR, 0);
        Intc_IntPrioritySet(APP_ECAP1_INT, 1, 0);

        Intc_SystemEnable(APP_ECAP1_INT);
    }

    Regards,

    Sylvain.

  • 0 in reply to Sylvain PALMERI
    Expert 1145 points

    Hi Melissa,

    The ISR is now fully functionnal. The initialization sequence describe in my previous post was correct, but I had several error into the code:

    1. the source code in the PRCM was wrong. I enabled PRUSS1 instead of PWMSS1, and 2. the APP_ECAP1_INT was declred in hexa instead of decimal.

    One think to notify, even if the core used is the C66x, we need to run the ARM to make the ecap counter running. I wasted a lot of time to debug before figure it out.

    Thanks for your time.

    Sylvain