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[TDA4M] CCS Setup failed .

Kenny Chiang
Prodigy 110 points
Other Parts Discussed in Thread: CCSTUDIO

We are planning to do some example check using CCS on TDA4 EVM board.

I follow the CCS Setup steps in "Processor SDK RTOS Automotive User Guide".

When I do the action in step 4, execute the load command in the scripting console.

It always failed and stuck at  Running the board configuration initialization from R5!

The error message is :

Error loading "/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/sciclient_ccs_init_mcu1_0_release.xer5f": Timed out after 20000ms while waiting for target to halt after an auto-run to "main (/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js#125) (/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js#125)

Is there some step missing in this user guide ?

I tried the CCS Setup steps in linux and windows environment and got the same error.

Windows 10 Professional 64 bit, Code Composer Studio version 9.1.0.00010

Ubuntu 18.04 64 bit, Code Composer Studio version 9.1.0.00010

  • 0
    TI__Guru 55685 points

    Hi Kenny,

    Have you update launch script: psdk_rtos_auto_j7_06_00_00_00\pdk\packages\ti\drv\sciclient\tools\ccsLoadDmsc\j721e\launch.js

    Please search for "edit this" to look at changes that need to be edited for your usage of this script.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Prodigy 110 points

    Hi Rishabh,

    Yes, I edited the path of pdkPath, ccs_init_elf_file and sysfw_bin in file launch.js.

    The messages in the scripting console window:

    Initializing .. (Completed)

    js:> load("/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js");
    Connecting to DMSC_Cortex_M3_0!
    Connecting to DMSC_Cortex_M3_0!
    Loading DMSC Firmware ... /home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/soc/V1/ti-sci-firmware-j721e-gp.bin
    DMSC Firmware Load Done...
    DMSC Firmware run starting now...
    Connecting to MCU Cortex_R5_0!
    Running the board configuration initialization from R5!
    Error loading "/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/sciclient_ccs_init_mcu1_0_release.xer5f": Timed out after 20000ms while waiting for target to halt after an auto-run to "main (/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js#125) (/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js#125)
    js:>

    And the status of MCU_Cortex_R5_0 and DMSC_COrtex_M3_0 are keeping to Running 

  • 0 in reply to Kenny Chiang
    TI__Guru 55685 points

    Hi,

    Can you share updated launch.js

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Prodigy 110 points

    Hi Rishabh,

    These are the content of file "launch.js"

    I marked the text that I modified with bold font.

    /*
    * Copyright (c) 2018-2019, Texas Instruments Incorporated
    * All rights reserved.
    *
    * Redistribution and use in source and binary forms, with or without
    * modification, are permitted provided that the following conditions
    * are met:
    *
    * * Redistributions of source code must retain the above copyright
    * notice, this list of conditions and the following disclaimer.
    *
    * * Redistributions in binary form must reproduce the above copyright
    * notice, this list of conditions and the following disclaimer in the
    * documentation and/or other materials provided with the distribution.
    *
    * * Neither the name of Texas Instruments Incorporated nor the names of
    * its contributors may be used to endorse or promote products derived
    * from this software without specific prior written permission.
    *
    * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    */

    //
    //File Name: launch_j721e.js
    //Description:
    // Launch the DMSC firmware and board configuration from R5F.
    //
    //Usage:
    //
    //From CCS Scripting console
    // 1. loadJSFile "C:\\ti\\launch_j721e.js"
    //
    //Note:
    // 1. Search for "edit this" to look at changes that need to be edited
    // for your usage.
    //


    //<!!!!!! EDIT THIS !!!!!>
    // Set this to 1 to allow loading the GEL files directly from the ccxml file.
    disableGelLoad = 0;
    // Set to 1 to use the firmware with Firewalls.
    if (disableGelLoad == 0)
    {
    //Path to GEL files
    gelFilePath = "k3-avv-repo/framework/gels/K3J7";
    }
    //PDK path. Edit this
    pdkPath = "/home/tda4dev/psdk_rtos_auto_j7_06_00_00_00/pdk";

    //path to board config elf
    ccs_init_elf_file = pdkPath+"/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/sciclient_ccs_init_mcu1_0_release.xer5f";

    //path to sysfw bin
    sysfw_bin = pdkPath+"/packages/ti/drv/sciclient/soc/V1/ti-sci-firmware-j721e-gp.bin";

    //<!!!!!! EDIT THIS !!!!!>

    // Import the DSS packages into our namespace to save on typing
    importPackage(Packages.com.ti.debug.engine.scripting)
    importPackage(Packages.com.ti.ccstudio.scripting.environment)
    importPackage(Packages.java.lang)
    importPackage(java.io);
    importPackage(java.lang);

    function updateScriptVars()
    {
    //Open a debug session
    dsMCU1_0 = debugServer.openSession( ".*MCU_Cortex_R5_0" );
    dsDMSC_0 = debugServer.openSession( ".*DMSC_Cortex_M3_0" );
    }

    function printVars()
    {
    updateScriptVars();
    }

    function connectTargets()
    {
    /* Set timeout of 20 seconds */
    script.setScriptTimeout(20000);
    updateScriptVars();
    sysResetVar=dsDMSC_0.target.getResetType(1);
    sysResetVar.issueReset();
    print("Connecting to DMSC_Cortex_M3_0!");

    /*The CCXML file automatically loads the GEL for now*/

    // if (disableGelLoad == 0)
    // {
    // // Load the GEL. This can be removed if the GEL is already linked with the target ccxml
    // dsDMSC_0.expression.evaluate('GEL_LoadGel("'+gelFilePath+'/J7_SVB.gel")');
    // }
    // Connect targets
    dsDMSC_0.target.connect();
    print("Loading DMSC Firmware ... " + sysfw_bin);
    // Load the DMSC firmware
    dsDMSC_0.memory.loadRaw(0, 0x40000, sysfw_bin, 32, false);
    print("DMSC Firmware Load Done...");
    // Set Stack pointer and Program Counter
    stackPointer = dsDMSC_0.memory.readWord(0, 0x40000);
    progCounter = dsDMSC_0.memory.readWord(0, 0x40004);
    dsDMSC_0.memory.writeRegister("SP", stackPointer);
    dsDMSC_0.memory.writeRegister("PC", progCounter);
    print( "DMSC Firmware run starting now...");
    // Run the DMSC firmware
    dsDMSC_0.target.runAsynch();
    print("Connecting to MCU Cortex_R5_0!");

    // Connect the MCU R5F
    dsMCU1_0.target.connect();

    print("Running the board configuration initialization from R5!");
    // Load the board configuration init file.
    dsMCU1_0.memory.loadProgram(ccs_init_elf_file);
    // Halt the R5F and re-run.
    dsMCU1_0.target.halt();
    // Run Synchronously for the executable to finish
    dsMCU1_0.target.run();

    /* Run the DDR Configuration */
    print("Running the DDR configuration... Wait till it completes!");
    dsDMSC_0.target.halt();
    dsDMSC_0.expression.evaluate("J7ES_LPDDR4_4266MTs_Config_Late()");
    dsDMSC_0.target.runAsynch();
    }

    function disconnectTargets()
    {
    updateScriptVars();
    // Disconnect targets
    dsDMSC_0.target.disconnect();
    // Reset the R5F to be in clean state.
    //dsMCU1_0.target.reset();
    }

    function doEverything()
    {
    printVars();
    connectTargets();
    disconnectTargets();
    print("Okay you are good to go.. Happy Debugging!");
    }

    var ds;
    var debugServer;
    var script;

    // Check to see if running from within CCSv4 Scripting Console
    var withinCCS = (ds !== undefined);

    // Create scripting environment and get debug server if running standalone
    if (!withinCCS)
    {
    // Import the DSS packages into our namespace to save on typing
    importPackage(Packages.com.ti.debug.engine.scripting);
    importPackage(Packages.com.ti.ccstudio.scripting.environment);
    importPackage(Packages.java.lang);

    // Create our scripting environment object - which is the main entry point into any script and
    // the factory for creating other Scriptable ervers and Sessions
    script = ScriptingEnvironment.instance();

    // Get the Debug Server and start a Debug Session
    debugServer = script.getServer("DebugServer.1");
    }
    else // otherwise leverage existing scripting environment and debug server
    {
    debugServer = ds;
    script = env;
    }

    doEverything();

  • 0 in reply to Kenny Chiang
    TI__Guru 55685 points

    Hi,

    It seems that Gel files are not getting loaded through ccxml.

    Can you please share a screenshot of CCS when this error occurs.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Prodigy 110 points

    Hi Rishabh,

    In the Processor SDK RTOS Automotive User Guide, it says that "Gel files are provided in the package" in the  

    Step 3.2.

    I cannot find any "J7_EVM.gel" file in the CSP that installed into CCS,

    so I use the gel file J721E_EVM.gel in the folder "ti/ccs910/ccs_base/emulation/boards/dra8x/gel"

    Regards,

    Kenny Chiang

  • 0 in reply to Kenny Chiang
    TI__Guru 55685 points

    Hi Kenny,

    I want to see the Console instead of Scripting Console.

    Yes you are correct, you have to use the gel file from the folder "ti/ccs910/ccs_base/emulation/boards/dra8x/gel".

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Prodigy 110 points

    The full messages in Console window are as below:

    DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
    DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
    DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
    DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
    DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
    DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
    DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
    DMSC_Cortex_M3_0: GEL Output: C66xx_0 configured for Wait In Reset Mode
    DMSC_Cortex_M3_0: GEL Output: C66xx_1 configured for Wait In Reset Mode
    DMSC_Cortex_M3_0: GEL Output: C71x_0 configured for Wait In Reset Mode
    DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
    DMSC_Cortex_M3_0: GEL Output: Power Domain: On
    DMSC_Cortex_M3_0: GEL Output: Module State: Enable
    DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 3 (CPSW9G PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 3 (CPSW9G PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 5 (Video PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 5 (Video PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 6 (GPU PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 6 (GPU PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 7 (C7x PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 7 (C7x PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
    DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
    DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x8000039F
    DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 13 (C66x PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 13 (C66x PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 15 (Audio 1 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 15 (Audio 1 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 18 (DSS2 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS2 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 19 (DSS3 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 19 (DSS3 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 23 (DSS7 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 23 (DSS7 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 25 (Vision PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 25 (Vision PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
    DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL)
    DMSC_Cortex_M3_0: GEL Output: MCU PLL 1 (MCU PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL)
    DMSC_Cortex_M3_0: GEL Output: MCU PLL 2 (MCU PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
    DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_AUDIO
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_ATL
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MLB
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MOTOR
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MISCIO
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_GPMC
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPFE
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPE
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_2
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_3
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC8B_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_I3C
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_2
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_3
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_4
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_5
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_2
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_2
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_3
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_9GSS
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TX_DPHY_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSI
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSITX_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_2
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_2
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0_PBIST
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1_PBIST
    DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed!
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_2
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_3
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCOM
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUPBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCORE
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SDE
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
    DMSC_Cortex_M3_0: GEL Output: WKUP/MCU clock selection and Pad configuration MMRs unlocked.
    DMSC_Cortex_M3_0: GEL Output: I2C Config Done Successfully...
    DMSC_Cortex_M3_0: GEL Output: VDD_CORE programmed to 0.9V.
    DMSC_Cortex_M3_0: GEL Output: I2C Config Done Successfully...
    DMSC_Cortex_M3_0: GEL Output: Waiting for I2C1 bus to be free...
    DMSC_Cortex_M3_0: GEL Output: Waiting for I2C1 transmit bit to be set...
    DMSC_Cortex_M3_0: GEL Output: Waiting for I2C1 ARDY bit to be set...
    DMSC_Cortex_M3_0: GEL Output: Waiting for RRDY bit to be set...
    DMSC_Cortex_M3_0: GEL Output: Waiting for ARDY bit to be set...
    DMSC_Cortex_M3_0: GEL Output: Register value in PMIC is: 0x39
    DMSC_Cortex_M3_0: GEL Output: Configuring drive strength.
    DMSC_Cortex_M3_0: GEL Output: First, unlock the MMRs.
    DMSC_Cortex_M3_0: GEL Output: Unlocked MMRs.
    DMSC_Cortex_M3_0: GEL Output: Configuring horizontal drive strength.
    DMSC_Cortex_M3_0: GEL Output: Horizontal drive strength configured.
    DMSC_Cortex_M3_0: GEL Output: Configuring vertical drive strength.
    DMSC_Cortex_M3_0: GEL Output: Vertical drive strength configured.
    DMSC_Cortex_M3_0: GEL Output: LVCMOS drive strength configured to 0xD
    MCU_Cortex_R5_0: Error connecting to the target: (Error -2062 @ 0x0) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.2.2.47)
    MCU_Cortex_R5_0: Error connecting to the target: (Error -2062 @ 0x0) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.2.2.47)

  • 0 in reply to Kenny Chiang
    TI__Guru 55685 points

    Hi,

    Have you set the board to "NO BOOT" mode?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 420 points

    Hi,

    sadly I seem to have the same problem here.

    For me it hangs at GEL Expression: OnTargetConnect().

    The console shows:

    DMSC_Cortex_M3_0: GEL Output: Configure_ATCM
DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
DMSC_Cortex_M3_0: GEL Output: Configure_RAT
DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to    [0x6000_0000, 0x4000_0000].
DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
DMSC_Cortex_M3_0: GEL Output: MCU_R5_Cluster_0_split
DMSC_Cortex_M3_0: GEL Output: MAIN_R5_Cluster_0_split
DMSC_Cortex_M3_0: GEL Output: MAIN_R5_Cluster_1_split
DMSC_Cortex_M3_0: GEL Output: Configure_C66x_Halt_Upon_PowerUp
DMSC_Cortex_M3_0: GEL Output: C66xx_0 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: C66xx_1 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: Configure_C71_Halt_Upon_PowerUp
DMSC_Cortex_M3_0: GEL Output: C71x_0 configured for Wait In Reset Mode
DMSC_Cortex_M3_0: GEL Output: Configure_R5F_Halt_Upon_PowerUp
DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Checking LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: Power Domain: On
DMSC_Cortex_M3_0: GEL Output: Module State: Enable
DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 3 (CPSW9G PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 3 (CPSW9G PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 4 (Audio 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 4 (Audio 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 5 (Video PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 5 (Video PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 6 (GPU PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 6 (GPU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 7 (C7x PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 7 (C7x PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80000FC9
DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 13 (C66x PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 13 (C66x PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 15 (Audio 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 15 (Audio 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 18 (DSS2 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 17 (DSS2 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 19 (DSS3 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 19 (DSS3 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 23 (DSS7 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 23 (DSS7 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 25 (Vision PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 25 (Vision PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 1 (MCU Peripheral PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 1 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 2 (MCU CPSW PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 2 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_ALWAYSON
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUG2DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUP_GPIO
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_WKUPMCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_DEBUG
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_MCAN_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_OSPI_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_HYPERBUS
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_I3C_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_ADC_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_R5_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU_PULSAR_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_ALWAYSON
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_AUDIO
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_ATL
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MLB
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MOTOR
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_MISCIO
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_GPMC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPFE
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_VPE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_DEBUG
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_2
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMTIMER_3
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC4B_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MMC8B_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_UFS_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SAUL
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PER_I3C
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_4
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_5
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_6
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_7
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_8
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_9
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_10
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_11
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_12
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_MCANSS_13
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_4
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_5
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_9GSS
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSS
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TX_DPHY_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DSI
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EDP_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSITX_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_PHY_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CSIRX_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C71X_1_PBIST
DMSC_Cortex_M3_0: GEL Output: ERROR: module state NOT changed!
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_CLUSTER_1_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_2
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A72_3
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCOM
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUPBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPUCORE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_C66X_PBIST_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DECODE_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ENCODE_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SDE
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMPAC_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_VPAC_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output: WKUP/MCU clock selection and Pad configuration MMRs unlocked.
DMSC_Cortex_M3_0: GEL Output: I2C Config Done Successfully...

    Than it hangs. When canceling and retrying to launch the js file it gets over this point but hangs later.

    The scripting console shows:

    js:> load("/home/REMOVED/psdk_rtos_auto_j7_06_00_01_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js")
Connecting to DMSC_Cortex_M3_0!
Connecting to DMSC_Cortex_M3_0!
Error connecting to the target: Timed out after 200000ms (/home/REMOVED/psdk_rtos_auto_j7_06_00_01_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js#105) (/home/REMOVED/psdk_rtos_auto_j7_06_00_01_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js#105)
js:> load("/home/REMOVED/psdk_rtos_auto_j7_06_00_01_00/pdk/packages/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js")
Connecting to DMSC_Cortex_M3_0!
Loading DMSC Firmware ... /home/REMOVED/psdk_rtos_auto_j7_06_00_01_00/pdk/packages/ti/drv/sciclient/soc/V1/ti-sci-firmware-j721e-gp.bin
DMSC Firmware Load Done...
DMSC Firmware run starting now...
Connecting to MCU Cortex_R5_0!
Running the board configuration initialization from R5!

    And the console shows:

    [MCU_Cortex_R5_0]  
DMSC Board Configuration with Debug enable 
 DMSC Firmware Version 19.6.1-v2019.06a-1-gb5a4f (Terr
 Firmware revision 0x13
 ABI revision 2.6
 
DMSC Board Configuration with Debug enable

    Now I don't know, is this OK?

    When select "connect to target" on the C77 I get an error:

    Error connecting to the target:
(Error -2081 - (0:0:0))
Device functional clock appears to be off. Power-cycle the board. If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK).
(Emulation package 8.2.2.47)

    Best regards

    Jan

  • 0 in reply to Jan Hieber
    TI__Guru 55685 points

    Hi Jan,

    This error usually occurs when board is set in a particular boot mode.

    Have you set the board to NO BOOT mode?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 420 points

    Yes I have.

    The switches are: 10001000 01110000

  • 0 in reply to Jan Hieber
    TI__Guru 55685 points

    Hi Jan,

    Can you confirm if you have alpha board or beta board?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 420 points

    Should be beta.

    To make sure, how can I identify it?

  • 0 in reply to Jan Hieber
    TI__Guru 55685 points

    Hi Jan,

    Can you tell me the CP number of board (look near SD card slot)?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 420 points

    The only number near the SD slot is a white label with 3419790065.

    Colleague told me it's a beta board.

  • 0 in reply to Jan Hieber
    TI__Guru 55685 points

    Hi Jan,

    Can you try commenting below piece of code from gel files:

    //Configure the PMIC voltage rail for VDD_Core to 0.9V to support LPDDR4 at 4266MT/s.
//First, unlock the WKUP/MCU domain Padconfig MMRs.
unlockWkupPads();
GEL_TextOut("WKUP/MCU clock selection and Pad configuration MMRs unlocked.\n");

//Configure the I2C bus, and write to the PMIC to set the output voltage for VDD_CORE to 0.9V.
Configure_Core_0v9();
GEL_TextOut("VDD_CORE programmed to 0.9V.\n");

//Check the configuration by reading back the values written to PMC.
temp = Read_VDD_Core_Config();
GEL_TextOut("Register value in PMIC is: %x\n",,,,, temp);

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points

    Hi Jan,

    The gel file to be modified is C:\ti\ccs901\ccs\ccs_base\emulation\boards\dra8x\gel\J721E_EVM.gel

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points

    Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 420 points

    I managed to get to the point where the console tells "happy debugging", so this works.

    When I debug a C66 project I get the following:

    C66xx_0: Error connecting to the target: (Error -1143 @ 0x0) Device core was hung. The debugger has forced the device to a ready state and recovered debug control, but your application's state is now corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 8.2.2.47) 
C66xx_0: Trouble Writing Memory Block at 0xc000000 on Page 0 of Length 0x7ff0: (Error -1060 @ 0xC000000) Device is not responding to the request. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.2.2.47) 
C66xx_0: File Loader: Verification failed: Target failed to write 0x0C000000
C66xx_0: GEL: File: /home/IBEO.AS/jahi/perception-benchmarking-suite/CCS_workspace/BenchmarkMAC_C66/Debug/BenchmarkMAC_C66.out: Load failed.

    Another question: How to I know the exact model of DSP in the SOC? Like TMS320C66xx.

    I guess I am using the wrong linker script. Maybe it is not yet contained in the CCS. Is there an example for the C66 and especially for the C7 DSP?

    Best regards

    Jan

  • 0 in reply to Jan Hieber
    TI__Guru 55685 points

    Hi Jan,

    Glad to know that you are able to connect.

    Can you please create a new thread for issues related to DSP and mark this one as resolved.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 420 points

    OK thanks for helping! At least I can connect to the target now :)

    Not sure how to close this thread...

  • 0 in reply to Jan Hieber
    TI__Guru 55685 points

    Hi Jan,

    You can mark the posts that helped you resolve your issue as "This resolved my issue" and close the thread.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points

    Hi Jan,

    I didn't see a new thread, were you able to resolve DSP related issues?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 420 points

    Hey,

    I started this:

    I cannot close this thread here because i didn't start it.

  • 0 in reply to Jan Hieber
    TI__Guru 55685 points

    Ok thanks.

    Regards,

    Rishabh