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AM3352: GPMC to Xilinx selectMAP interface

William Sung36
Intellectual 395 points
Part Number: AM3352

Hi,

I am looking at a design where the TI AM3352 will be the small controller that will download the bitstream (configuration file) into a Xilinx 7 series FPGA. To speed up the bitstream download, i can use the selectMAP interface on the Xilinx 7 FPGA. The selectMAP interface is a 16 bit wide data bus with no address bus. It is a synchronous interface with a CLK, CS and WE signals. The configuration data (16 bit wide) is latched in on the rising edge of each clock cycle. Can the TI AM3352's GPMC be configured to support the selectMap interface? More details of the selectMAP interface can be found on Xilinx's document UG470.

As this is a common interface, i think someone must have asked this before on the forums but i was not able to find any details on it.

Thanks

  • 0
    TI__Guru**** 393215 points

    Hi,

    No, GPMC cannot be used for this purpose. Please check the GPMC timing diagrams in section 7.7.1 of the AM335x Datasheet Rev. K.

  • 0 in reply to Biser Gatchev-XID
    Intellectual 395 points

    Hi,

    What if i use the nWE signal as a clock for the 16 bits of data? If i look at figure 7-46 on spruh73p, the timing for a asynchronous single write access timing. The FPGA bitstream download interface does not have a address bus only a 16 bit wide data bus. If i latch the data into the FPGA with the nWE signal as the clock and do not connect the address then this should work by looking at the timing diagram. 

    Doing it this way will be slower as i am wasting time during the address cycle. What is the minimum time that i do do a complete write cycle in? Is it 45ns  (tWPmin + tWPH) as shown in the timing diagram or can this be shortened?

    Thanks

  • 0 in reply to William Sung36
    TI__Mastermind 30140 points

    Hi,

    I think you might be able to use GPMC for this type of parallel interface.

    The GPMC configuration is very flexible. The bit-fields in the GPMC_CONFIGn registers determine which counter cycle control signals like WEn change state. The counters increment with the internal GPMC_FCLK.

    The tWP and tWPH in Figure 7-46 are set to satisfy the timing requirements outlined in Table 7-44. The parameters WEOnTime and WEOffTime determine when the WEn signal goes low and high, respectively. The low pulse of WEn could be reduced to 1 FCLK cycle, which on AM335x should be 10ns.

    You might even be able to force the GPMC to skip the address cycle by bringing in the WEOntime and setting the WRDATAONADMUXBUS field to be early in the write cycle.

    I can help you to hand tune the GPMC registers, but it would help to get access to the GPMC bus so you can observe the signals with a scope. Through a bit of trial and error, you can get the waveform you need, and have margins for the timings required by the FPGA.

    Regards,
    Mark