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CC1310: Pin#16/DIO_10 Pulses immediately after reset

Part Number: CC1310

We are noticing a ~1us wide strong negative pulse about 1ms after reset completes (Logic L->H transition).  this is causing a problem with an external watchdog device.  Is there a way to suppress this?  this isn't a "glitch as it is clear the I/O cell is acting a totem-pole output and strongly pulling down (we tried a 1K pull up and the signal was still there).

We are assuming this is some type of "auto-detect" for some port.  Can this be inhibited?  This is before our code is even installed.

  • Hi Mark,

    We will look into this and get back to you ASAP.

    Thanks,

    Alexis

  • Hi,

    Could you please isolate the pin (Pin#16/DIO10) from the rest of the Circuit and try again?

    If there is no code on CC1310 then all the DIOs must be in a Tri-State in a power-up condition.

    Thanks,

    PM

  • We already have.  We cut the trace, and when we did, the output went from a logic-0 to a Logic-1 (step) (nothing connected but an oscilloscope probe). 

    It seemed like normal logic levels, not floating. (the step waveform observed)

    When connected - the output is normally connected to a Microchip MCP1316M Watchdog chip which has an internal 52K pull-up resistance.

    Mark W

  • Hi,

    Could you please Erase the chip and try again? Just I want o make sure No program is on the Chip.

    How many boards you  tested? Does it happen on all the boards?

    Do you have our CC1310 Launchpad?

    If you have it, could you please test it? You may need to Erase the chip also.

    Thanks,

    PM

  • Yes, my boss who has been working with this chip for about 2+ years had erased the chip (same concern you had) and got the same results.  It is happening on at least 2 boards that perform fine otherwise once they get the program on it (disabling the watchdog chip).  The problem is after the RESET returns to Logic-1.

    -Mark W

  • Hi Mark,

    Bootloader uses the pin (DIO10) as part of SSI bus until it get a valid image. Please see the following table.

    Please refer to section 8.2.2 of TRM for more details.

    Thanks,

    PM

  • Yeah, I'm aware of that table, but thought that until we tried to load our code, that I/O Line would be silent.  We usually load code using the UART0. 

    I suspect we are out of luck.

    -Mark W

  • Hi,

    No, it checks both UART and SSI buses until it gets the image from one of those interface. Please see the following text form the TRM.

    "The bootloader selects the interface that is the first to be accessed by the external device. Once selected,

    the TX output pin for the selected interface is configured; the module on the inactive interface (UART0 or

    SSI0) is disabled. To switch to the other interface, the CC26x0 and CC13x0 devices must be reset."

    Thanks,

    PM

  • We didn't "select" an interface yet (by transmitting data at it). All the other SSIO pins have nothing connected to them.  Is just having a pull-up causing the problem, or is the chip going to "test" that I/O line (DIO_10) no mater what?  The pull-up is there during the RESET time so there is NO activity on the DIO_10 line from our circuitry.

    -Mark W

  • Hi,

    It monitors both SSI and UART interfaces until it gets the valid Image. Until that you can't use that interface.

    Thanks,

    PM