OMAP-L138 timer interrupt priority

Hi Deepak,

Are you referring to Linux when specifying the "RT-Preempt patch"? If so, this question may be answered more thoroughly in the Linux forum. A list of embedded software forums can be found here: http://e2e.ti.com/support/embedded/default.aspx

As for other ways, you can modify the INTMUX registers of the DSP interrupt controller to set the priority of system interrupts (Timer 2 and Timer3). There are a total of 12 available CPU interrupts (CPUINT4 - CPUINT15) and the order of the CPU interrupts determines the priority for pending interrupts. Thus if you would like Timer 2 and Timer 3 to have the highest priority, you can map their respective system interrupts to CPUINT4 and CPUINT5. For more details, please refer to Ch. 7 of the C674x DSP Megamodule Reference Guide: http://www.ti.com/lit/pdf/sprufk5

Hope this helps!

-Kevin

*EDIT*

The above mentioned is for the DSP only. For the ARM, you can use the ARM interrupt controller to prioritize system interrupts. Channels 0 and 1 map the the ARM FIQ and Channels 2 - 31 map to the ARM IRQ. The lower the channel, the higher the priority. If two or more system interrupts are mapped to the same channel, the system interrupt with a lower number has higher priority. For more details, please refer to Ch.12 of the System Reference Guide. http://www.ti.com/lit/pdf/sprugm7

Hi Kevin,

Thank you for the answer.

I am using a Linux kernel with RT_-Preempt patch and  the timer priority which I want to increase is in ARM control.

As per your suggestion I will try and let you know the outcome.

Regards,

Deepak

Hi Kevin,

I am developing an application which uses timer2, timer3 and modified davinci emac ethernet driver. The data from davinci emac is time critical so it will have a highest priority followed by the timers ISR.

Please find below the steps which I am about to implement in my application to increase the interrupt priority

1. Enable ENABLE bit in GER

2. Enable IRQ by setting bit 1 in HIER

3. Enable the system interrupt for

• 33 - EMAC_C0RXTHRESH EMAC 
• 34 - EMAC_C0RX EMAC
• 35 - EMAC_C0TX EMAC
• 36 - EMAC_C0MISC
• 68 - T64P2_ALL
• 96 - T64P3_ALL 

   by writing these values into EISR

4. Add interrupts to channel

• Emac interrupts: 33 to 36 in channel 2
• Timer interrupts: 68 to 96 in channel 3

   by writing 0x36353433 in CMR2 and 0x6896 in CMR3

Am I missing any of the steps? If I want to implement nesting and vectorization, how to calculate the address of ISR and store it in VBR and VSR?

If there is any sample application which has implemented any of the AINTC methodology please point to the same.

Thanks & Regards,

Deepak

Deepak,

Kevin created a bundle of simple examples which include interrupts on this wiki here: http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL

-Tommy