Hi,
DSP communicate with FPGA with SRIO. FPGA sends a doorbell to dsp after sending data (about 4ms). FPGA writes different values in doorbell info and DSP operates depending on the value of the ICSR register. But when fpga write 0001 and 0010 respectively, the value of ICSR is 6. That is to say, ICS1 and ICS2 receive interrupt request at the same time. What may cause that？
