TMS320C6678: C6678 Srio 4x link 1x

Hi,

What is software you used to configure SRIO? Is it TI Processor SDK RTOS for C6678? There are code examples to configure x4 or 2x2 or other mode,

int32_t setSrioLanes (CSL_SrioHandle hSrio, srioLanesMode_e laneMode)
{
Uint8 port, pathMode;
Uint8 bootCompleteFlag;
#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(SOC_K2K) && !defined(SOC_K2H)
Uint32 serdesTXConfig;
Uint32 msyncSet = 0x00100000;
#endif

CSL_SRIO_GetBootComplete (hSrio, &bootCompleteFlag);

if (bootCompleteFlag == 1)
/* Set boot complete to be 0; to enable writing to the SRIO registers. */
CSL_SRIO_SetBootComplete (hSrio, 0);

/* Set the path mode number to the lane configuration specified */
switch (laneMode)
{
case srio_lanes_form_four_1x_ports: /* four 1x ports (forms ports: 0,1,2 and 3) */
pathMode = 0;
break;
case srio_lanes_form_one_2x_port_and_two_1x_ports: /* one 2x port and two 1x ports (forms ports: 0, 2 and 3) */
pathMode = 1;
break;
case srio_lanes_form_two_1x_ports_and_one_2x_port: /* two 1x ports and one 2x port (forms ports: 0, 1 and 2) */
pathMode = 2;
break;
case srio_lanes_form_two_2x_ports: /* two 2x ports (forms ports: 0 and 2) */
pathMode = 3;
break;
case srio_lanes_form_one_4x_port: /* one 4x port (forms port: 0) */
pathMode = 4;
break;
default: /* Invalid lane configuration mode specified */
return -1;
}

/* Configure the path mode for all ports. */
for (port = 0; port < 4; port++)
{
/* Configure the path mode for the port. */
CSL_SRIO_SetPLMPortPathControlMode (hSrio, port, pathMode);
#if !defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(SOC_K2K) && !defined(SOC_K2H)
/* Get the current SERDES TX config */
CSL_BootCfgGetSRIOSERDESTxConfig (port,&serdesTXConfig);

/* Determine the MSYNC bit's setting according to laneMode being used */
switch (laneMode)
{
case srio_lanes_form_four_1x_ports: /* four 1x ports (forms ports: 0,1,2 and 3) */
msyncSet = 0x00100000;
break;
case srio_lanes_form_one_2x_port_and_two_1x_ports: /* one 2x port and two 1x ports (forms ports: 0, 2 and 3) */
msyncSet = (port != 1 ? 0x00100000 : 0xFFEFFFFF);
break;
case srio_lanes_form_two_1x_ports_and_one_2x_port: /* two 1x ports and one 2x port (forms ports: 0, 1 and 2) */
msyncSet = (port != 3 ? 0x00100000 : 0xFFEFFFFF);
break;
case srio_lanes_form_two_2x_ports: /* two 2x ports (forms ports: 0 and 2) */
msyncSet = (((port != 1) && (port != 3)) ? 0x00100000 : 0xFFEFFFFF);
break;
case srio_lanes_form_one_4x_port: /* one 4x port (forms port: 0) */
msyncSet = (port == 0 ? 0x00100000 : 0xFFEFFFFF);
break;
default: /* Invalid lane configuration mode specified */
return -1;
}

/* Set msync for each port according to the lane mode (port width) specified */
if (msyncSet == 0x00100000)
serdesTXConfig |= msyncSet; /* Set MSYNC bit */
else
serdesTXConfig &= msyncSet; /* Clear MSYNC bit */

/* Write SERDES TX MSYNC bit */
CSL_BootCfgSetSRIOSERDESTxConfig (port, serdesTXConfig);
#endif
}

#if defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(SOC_K2K) || defined(SOC_K2H)
serdes_setSrioLanes(hSrio,laneMode);
#endif

if (bootCompleteFlag == 1)
/* Set boot complete back to 1; configuration is complete. */
CSL_SRIO_SetBootComplete (hSrio, 1);

return 0;
}

Did you follow this but you only get 1x lane?

Regards, Eric