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TMDSIDK437X: DDR3 layout questions

Part Number: TMDSIDK437X

Hello community,

I have a few questions regarding the IDK AM437x dev board. We are developing a custom board based on this dev board and we are experiencing issues related to the external DDR (MT41K256M16TW-107). According to the data sheet, the MT41K256M16HW-107 should be backward compatible with the MT41K256M16HA-125, however we have still carefully adjusted the timings in the TI spreadsheet  tool in order to configure the RAM correctly.
In order to test simple read/write functions, we have created a small GEL function that iterates over several addresses and writes a certain value to the specific address. After writing, the value is read back multiple times. While the first few read iterations (where the number of iterations seems to be a random number that can vary between just 100 reads up to 1000 reads) show the correct value, at one point the values drop to 0x0.
According to the 0's would indicate that the RAM is non-existent, whereas changing values indicate the RAM is configured incorrectly.
When I switch to the memory browser view in CCS, I see certain (but not all) values changing after refreshing the view.
In order to exclude power failure as possible cause, we have checked the 0.75 and 1.5 V and they are proper.
Now we are looking for possible causes that might lead to a loss of signal integrity, and we stumbled across a few questions:
- On the dev board, are the via stubs back-drilled? According to they should be back-drilled if longer than 15mils (or 0.38mm)  in the case of high-speed applications. In our case, we decided to avoid back-drilling. I guess that we can exclude this as a possible cause for the loss of signal integrity if back-drilling was also avoided on the dev-board
- What is the size of the annular rings and the pcb trace width on the dev board? Could you imagine that our issues arise from too thin annular rings?
- As a side note: We have a trace length mismatch of 1mm between CLK and nCLK, and we assume that this might be the main cause of the issues. However, we would like to exclude every other potential cause before ordering a new PCB.

Our team is thankful for any advice!

Best,

Liliane

  • Hi Liliane, I'm not sure on some of the specific questions on the IDK, i will have to investigate those.

    While the app note you found is good, more applicable DDR layout design rules can be found in the AM437x datasheet in section 5.12.8.2.  Ensure that you have followed all of the layout guidelines in this section.  Table 5-58 shows a maximum CK skew of 5mils (0.127mm), so this is way out of spec.  As you say, this along with other factors, may be contributing to the issues you are seeing.

    One more applicable high speed layout app note can be found on the AM437x product page: High Speed Interface Layout Guidelines (SPRAAR7)

    To see if we can get your current board working, we can see if you have the correct configuration:

    Can you run the following DSS script via JTAG:  git.ti.com/.../am43xx-ddr-analysis.dss

    Instructions for running in CCS can be found here:  git.ti.com/.../README

    The script will parse the EMIF registers to help decode your configuration.  Also, can you send your completed spreadsheet.

    Regards,

    James