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66AK2H06: Questions for hardware design

Koichiro Tashiro
Mastermind 22945 points
Part Number: 66AK2H06

Hi,

I have questions from customer for 66AK2H06 hardware design.

Q1) Customer is planning to use only DDR3A. DDR3B is un-used.
According to sprabv0.pdf, section 6.8.3, only clock inputs (DDR3BCLKN, DDR3BCLKP) and VREFSSTL(DDR3BVREFSSTL) need to be taken care.
http://www.ti.com/lit/an/sprabv0/sprabv0.pdf

Other signals below are must be left floating, correct?







Q2) What is min. and max. voltage for VBUS input?

Q3) VCL and VD pins are not used in customer system as SmartReflex is done by VCNTLx pins.
What is recommended pin configuration for VCL and VD when un-used?

Q4) What is MAINPLLODSEL(GPIO14) function?

Q5) I guess AVSIFSEL[0:1] are used to select AVS(SmartReflex) interface.
It seems default values are 00. What below description means? Does user need to configure something?



Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Guru**** 161600 points

    Hi Koichiro,

    Q1). Yes, your understanding is correct.

    Q2). USBVBUS should be 5.0V. Exact Min/Max values can be seen in USB3.0 standards and OTGv2.0 standards.

    Q3). You can check EVMK2H, these signals are routed to CN19 and are unconnected.

    Q4). It enables the boot rom to configure the main PLL divider.

    Q5). Again you can refer to EVMK2H schematics for this one.

    Best Regards,
    Yordan