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Original question:

HyperLink priority field (PRI) in Control Word header

TMS320C6678: TMS320C6678: Hyperlink SerDes ambiguous configuration specs!

Daniel Costin
Intellectual 610 points
Part Number: TMS320C6678

Hi,

    1. The sprugw8c.pdf manual, Hyperlink User Guide for C66x, specifiesthat to obtain a specific PLL output (3.125 Ghz or 2.1 GHz, ....) it must set the MPY field based on reference clock value.

     Example: CFGPLL[8:1] MPY = 40(10x)for 312.50MHz input clock, 80(20x)for 156.25MHz, 50(12.5x) for 250MHz to get max speed 3.125GHz

     BUT how can be read the reference clock to know the calculated MPY value if you target a specific PLL output?

   . 2. The same manual species that PLL_BANDWIDTH = REFCLK/BWSCALE. In the table 2-4 it says that for PLL_OUTPUT=3.15GHz and for a medium bandwidth BWSCALE=13 ass PLL_BANWIDTH=REFCLK/13.

        Considering that REFCLK can have 3 different values, how can be this table valid?

       What is this BWSCALE used for as no register map it?

     Could you also respond to https://e2e.ti.com/support/processors/f/791/p/842860/3119561#3119561 ticket as the wrong manual specifications blocks use for writing the Hyperlink driver.

Thank you,

   Daniel.

  • 0
    TI__Guru* 95265 points

    Hi,

    1)

    PLL_OUTPUT=REFCLK*MPY

    LINERATE=REFCLK*MPY/RATESCALE

    The PLL_OUTPUT value must be in the 1.5625 GHz to 3.125 GHz range. For your own system, you know the REFCLK (156.25, 250 or 312.5), you have your target rate (this is the LINERATE). Then you can find out the MPY and RATESCALE.

    2) From HYPERLINK_SERDES_CFGPLL

    Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock input to the PLL is translated
    into the PLL output and impairs the ability of the transmitter and receiver to work properly. The loop
    bandwidth setting allows The user to select the setting that will reduce the jitter as much as possible in the PLL
    output. For most systems, medium bandwidth will be the best setting. All systems should start with medium
    bandwidth, and move to other values only when required to improve signal integrity.
    00b = Medium Bandwidth (Recommended)
    01b = Ultra High Bandwidth
    10b= Low Bandwidth
    11b= High Bandwidth

    a setting that provides a PLL
    bandwidth in the 8-30 MHz range must be chosen. The PLL bandwidth is defined by
    the following equation:
    PLL_BANDWIDTH = REFCLK/BWSCALE

    From Table 2-4: PLL Loop Bandwidth Selection. And PLL_BANDWIDTH = REFCLK/BWSCALE. Assume you use medium bandwidth and your PLL_OUTPUT is 1.5625Gbps, then your BWSCALE is 16. To get PLL_BANDWIDTH 8-30MHz, the REFCLK must be 8-30*16 = 128- 480MHz range. so you can use either of 156.25, 250 or 312.5MHz REFCLK.

    Regards, Eric

  • 0 in reply to lding
    Intellectual 610 points

    Hi Eric,

      So the entire configuration must be done knowing the value of external clock from inputs pins MCMCLKp, MCMCLKn. Do we have any status register that could be read for identifying this clock value or it must be assumed as external requirement?

    Daniel

  • 0 in reply to Daniel Costin
    TI__Guru* 95265 points

    Hi,

    You must know the external clock frequency yourself (like use a scope), this can't be read out from registers on the SOC.

    Regards, Eric