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AM5728: McASP5: RCKFAIL errors when McASP used as SLAVE (ACLKR, AFSR as output, AXR0 as input)

AnBer
Mastermind 30210 points
Part Number: AM5728


Team,

[I just EDITED the message to clarify the use case]

The McASP5 is used as a RCV only interface using 3 pins (ACLKR, AFSR as output, AXR0 as input)
The use case we want to implement is "4.1.1.1 ADC as Clock Master" from:
“McASP Design Guide - Tips, Tricks, and Practical Examples – SPRACK0” at http://www.ti.com/product/AM5728/technicaldocuments

We constantly received the RCKFAIL errors. No data seen at all on AXR0.
MCASP_RXCLKCHK register RCNT is always 0.
We have changed the boundaries inside this register and we cannot remove the RCKFAIL in the MCASP_RXSTAT unless we set the boundaries (MCASP_RXCLKCHK) min to 0x00 and max to 0xFF.
In this case the RX continues not working and we see the RCNT inside the MCASP_RXCLKCHK with 0x00 value.

Timings and signal intergrity on ACLKR are ok.

We already looked at:
https://e2e.ti.com/support/processors/f/791/p/710519/2656155#2656155
that gives somes steps to check (pinmux settings, ACLKR present during McASP init ..etc).

-What would the RCKFAIL error means for our specific use case?
-Are there some other things to check to help the debugging?

-Are there more consideration linked to BURST mode, FIFO usage and internal port usage for this use case?

-Do we have some existing examples for this use case that could be run on the AM5728 EVM (or X15 base board)?
-For example do we have a modified CSL DeviceLoopback_ExampleProject example that would use 2 McASP with external loopback (ie wire on the pins)?
http://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#id193
The idea is to test the use case 4.1.1.1 ADC as Clock Master from 'McASP Design Guide - Tips, Tricks, and Practical Examples' from the existing CSL example.
What would need to be modified?

Thanks in advance,

A.

  • 0
    TI__Mastermind 30210 points

    Team,

    Any inputs you can provide?

    Thanks in advance!

    A.

  • 0 in reply to AnBer
    TI__Mastermind 30140 points

    Hi AnBer,

    Sorry for the delay in responding.

    From your description (ACLKR, AFSR as output, AXR0 as input) it sounds like you are using McASP as described in SPRACK0 Section 4.1.1.2 ADC as Clock Slave. Can you confirm the bit clock and word clock are outputs to the other device (codec)? Is the other device receiving the necessary MCLK? How are you generating the clocks?

    If the timings are ok, then you must be able to observe the bit clock and frame sync coming from the AM572 McASP to the other device (codec).

    Information about RCKFAIL can be found in TRM section 24.6.4.15.6 Clock Failure Detection - there is a procedure outlined there. TRM section 24.6.4.15.6.3 Receive Clock Failure Check and Recovery explains the mechanics of the RCKFAIL logic.

    Can you confirm GBLCTL is being read back until the bits that were written are successfully latched?
    Before performing McASP global initialization, If external clock ACLKR is used, it must be running already for proper synchronization of the MCASP_GBLCTL register

    How are you servicing McASP traffic? CPU polling, DMA, interrupts?
    Try getting CPU polling to work first. See TRM Figure 24-137. McASP Polling Reception Method

    Are you receiving 16-bit words or 32-bit words?

    Are you reading from the appropriate bus?
    See TRM section 24.6.4.10 Data Transmission and Reception
    and TRM section 24.6.4.10.1.2 Receive Data Ready
    Data must be written to or read from the address consistent with the programming of XBUSEL/RBUSEL: When XFMT.XBUSEL=1 (or RFMT.RBUSEL=1), the config port address should be used. For XBUSEL=0 (or RBUSEL=0), the DMA port address should be used.

    Regards,
    Mark