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AM3358: Watchdog control

Part Number: AM3358
Other Parts Discussed in Thread: TMS320F2837

How to replace the following code:

EALLOW;

CpuTimer0Regs.TCR.bit.TRB = 1;

EDIS;

for AM3358? This comes from a repository for TMS320F2837x. The whole function is

Status_Type watchdog_stop

(

uint32_t key

)

{

if((watchdog_key == 0) || (key != watchdog_key)) { return Status_Failure; }

if(watchdog_timer == NO_TIMER_ID) { return Status_Failure; }

Hwi_disable();

/* Stop the timer */

Timer_stop(watchdog_timer);

Hwi_enable();

// EALLOW;

// CpuTimer0Regs.TCR.bit.TRB = 1;

// EDIS;

return Status_Success;

}

Thanks

Thanks

  • I know TCR.TRB bit, set to 1 to reload 32 bit counter (TIM) with PRD and 8 bit pre-scalar (PSC) with TDD for TMS320F2837x. What should I do to reload timer for AM3358.? Thanks

  • Hi Anping,

    I am not familiar with TMS320F2837x device, thus I can not advice for it.

    Anping Chen said:
    What should I do to reload timer for AM3358.?

    The current timer value can be accessed on-the-fly by reading the watchdog timer counter register (WDT_WCRR), modified by accessing the watchdog timer load register (WDT_WLDR) (no on-the-fly update), or reloaded by following a specific reload sequence on the watchdog timer trigger register (WDT_WTGR).

    After reset generation, the counter is automatically reloaded with the value stored in the watchdog load register (WDT_WLDR).

    When a watchdog timer is enabled, software must periodically trigger a reload before the counter overflows. Hence, the value of the WDT_WLDR[31:0] bit field must be chosen according to the ongoing activity preceding the watchdog reload.

    To reload the timer counter and reset the prescaler before reaching overflow, a reload command is executed by accessing the watchdog timer trigger register (WDT_WTGR) using a specific reload sequence. The specific reload sequence is performed whenever the written value on the WDT_WTGR register differs from its previous value. In this case, reload is executed in the same way as an overflow autoreload, but without the generation of a reset pulse. The timer counter is loaded with the value of the watchdog timer load register (the WDT_WLDR[31:0] TIMER_LOAD bit field), and the prescaler is reset.

    For more details, refer to AM335x TRM, ch 20.4 WATCHDOG

    Regards,
    Pavel

  • Hi Pavel

         I am still confused. Can you provide a snapshot of code to stop the timer and reload timer for AM3358? The code for TMS320F2837x device is the following 

    Hwi_disable();

    /* Stop the timer */

    Timer_stop(watchdog_timer);

    Hwi_enable();

    /* reload the timer */

    // EALLOW;

    // CpuTimer0Regs.TCR.bit.TRB = 1;

    // EDIS;

    Thanks

  • Anping,

    I have found something related to WDTimer in RTOS package, that might be useful for you. Please check below files:

    pdk_am335x_1_0_15/packages/ti/starterware/include/wdt.h
    pdk_am335x_1_0_15/packages/ti/starterware/dal/wdt.c
    pdk_am335x_1_0_15/packages/ti/starterware/examples/wdt/cpu_reset/cpu_reset_app_main.c
    pdk_am335x_1_0_15/packages/ti/starterware/examples/wdt/wdt_app.c

    Also we have WDTimer source code you can refer to in our u-boot. You can access u-boot source code from within PSDK Linux.

    u-boot-2019.01/drivers/watchdog/omap_wdt.c

    u-boot-2019.01/arch/arm/include/asm/ti-common/omap_wdt.h

    Regards,
    Pavel