Hi,
There is the NOTE below in the section 24.9.4.3.1.1 PCIe Controller Master Port to MMU Routing on page 6284 in AM572x TRM.
In order, for PCIe_SS1 and PCIe_SS2 master traffic to be routed through the MMU2, the
CTRL_MODULE_CORE bits: CTRL_CORE_SMA_software_7[13]
PCIE_SS1_MMU_ROUTE_ENABLE and CTRL_CORE_SMA_software_7[12]
PCIE_SS2_MMU_ROUTE_ENABLE, must be set to 0b1 by user software.
On the other hand, according to the description of CTRL_CORE_SMA_SW_7 register on page 4960, the bit 8 should be “PCIE_SS1_MMU_ROUTE_ENABLE”, not bit 13.
Q1 : Is CTRL_CORE_SMA_software_7 described in page 6284 the same as CTRL_SMA_SW_7 in page 4960 ?
Q2 : Which bit field is correct bit 13 or bit 8 in order to use MMU2 of PCIe_SS1 ?
Thanks and regards,
Hideaki
