AM5728: PCIe RC issue

Hideaki Matsumoto

Part Number: AM5728
Other Parts Discussed in Thread: XIO2001,

Hi,

The customer is struggling to use PCIe as RC on AM5728 for communicating with XIO2001 as Bridge (EP).

They found the Received Master Abort (bit 29) in the both PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER and PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS.

What’s difference of this bit between these two registers ?

They monitored the Received Master Abort was “0b0” in PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER, but the Received Master Abort was “0b1” in PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS register.

Thanks and regards,

Hideaki

over 6 years ago

0 -DK- over 6 years ago

TI__Mastermind 27890 points

Hi,

I'll need to confer with the Designer on this. He is on vacation until next week so the response will be delayed.

0 Hideaki Matsumoto over 5 years ago in reply to -DK-

TI__Genius 9200 points

Hi,

Thanks for your reply. Please let me know once the Designer came back from his vacation.

Thanks and regards,
Hideaki

0 -DK- over 5 years ago in reply to Hideaki Matsumoto

TI__Mastermind 27890 points

Thank you for your patience. From the designer:

The Master Abort bit is used to indicate that the RC got a Unsupported Request (UR) from an EP. The PCIe standard excerpt shown below indicates that master abort could be 1’b0 in the PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER but it could be 1’b1 in PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS register if the UR originated in the far side of a PCIe switch.

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AM5728: PCIe RC issue