Hi:
My customer says that Adeneo CE6.0 BSP for AM3517 was set up to use only 128MB although the LogicPD board has 256MB. Does the WINCE 6.0 R3 Software Development Kit (SDK) support 256MB or are we still restricted to 128MB ?
Thanks,
Pradhyum
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Hi:
My customer says that Adeneo CE6.0 BSP for AM3517 was set up to use only 128MB although the LogicPD board has 256MB. Does the WINCE 6.0 R3 Software Development Kit (SDK) support 256MB or are we still restricted to 128MB ?
Thanks,
Pradhyum
There are several version of boards with 128 MB and that is why "TI BSP" was released this way. It is very easy to setup for 256 MB and your customer can do the change themselves. We may address this issue in future releases by configuring more memory for certain version of boards
Atul
This issue is being tracked as SDOCM00077417.
(If the link does not work please flush your browser cache and try again).
Jatin/Atul:
Is there a recipe that the customer can follow to accomplish this ?. My understanding from customer is that there is inadequate documentation on this topic for Win CE.
Thanks,
Pradhyum
Here are the changes required to switch to 256MB memory:
1. Image_cfg.h: change the mapping for the RAM and DISPLAY
#define IMAGE_WINCE_RAM_CA 0x83000000
#define IMAGE_WINCE_RAM_SIZE 0x0C000000
#define IMAGE_WINCE_DISPLAY_CA 0x8F000000
#define IMAGE_WINCE_DISPLAY_SIZE 0x01000000
2. addrtab_cfg.inc, adding 128MB to the SDRAM(first entry in the table)
DCD 0x80000000, 0x80000000, 256 ; SDRAM
Thanks,
Tao
Also you need to change the following in addrtab_cfg.inc
g_oalAddressTable
DCD 0x80000000, 0x80000000, 256 ; SDRAM
DCD 0x94000000, 0x11000000, 16 ; CS2, NOR flash
DCD 0x95000000, 0x15000000, 16 ; CS5, LAN9311
DCD 0x96000000, 0x48000000, 16 ; L4 Core/Wakeup registers
DCD 0x97000000, 0x49000000, 1 ; L4 Peripheral
DCD 0x97100000, 0x68000000, 16 ; L3 registers
DCD 0x98100000, 0x6C000000, 16 ; SMS registers
DCD 0x99100000, 0x6D000000, 16 ; SDRC registers
DCD 0x9a100000, 0x6E000000, 16 ; GPMC registers
DCD 0x9b100000, 0x40200000, 1 ; 64KB SRAM
DCD 0x9b200000, 0x5C000000, 16 ; IPSS interconnect
DCD 0x9C200000, 0x00000000, 1 ; ROM
DCD 0x9C300000, 0x08000000, 1 ; NAND Registers (FIFO)
DCD 0x00000000, 0x00000000, 0 ; end of table
-Madhvi
The solution is not working, I use the sample AM35x_OSDesign, only change addrtab_cfg.inc and image_cfg.h in the C:\WINCE600\PLATFORM\AM35x_BSP\SRC\INC folder. rebuild the image, the image can not download to the board. here is the message:
-------------------------------------------------------------------------------
Main Menu
--------------------------------------------------------------------------------
[1] Show Current Settings
[2] Select Boot Device
[3] Select KITL (Debug) Device
[4] Network Settings
[5] SDCard Settings
[6] Set Device ID
[7] Save Settings
[8] Flash Management
[9] Enable/Disable OAL Retail Messages
[a] Select Display Resolution
[0] Exit and Continue
Selection: 0
Init HW: controller RST
SDCARD: reqested speed 1000000, actual speed 1000000
SDHC: command response timeout CTO!
MMC::MMCCommandResponse: MMCSendCommand error, command = 8
MMC::MMCCommandResponse: Command Response Error
SDCARD: reqested speed 25000000, actual speed 19200000
BLSDCardReadLogo: cannot open Logo.bmp
BL_IMAGE_TYPE_BIN
Download file information:
-----------------------------------------------------------
[0]: Address=0x0c000000 Length=0x024f9ebc Save=0x80002000
-----------------------------------------------------------
Download file type: 1
I also tried to set IMGRAM64=1 and rebuild, it is still gives the same message.
Feng jiang,
The address(=0x0c000000) does not seem to be a valid address to download.
Eboot is expecting address at IMAGE_WINCE_CODE_CA for NK.bin that compiled without IMGNAND variable.
Please share your image_cfg.h if your changes are different from what is listed in this post.
Thanks,
Tao
HI Tao, I did not set IMGNAND variable when build the image. Here is the image_cfg.h file used according your recommendation.
Let me know if you need more info.
Thanks
// All rights reserved ADENEO EMBEDDED 2010
/*
================================================================================
* Texas Instruments OMAP(TM) Platform Software
* (c) Copyright Texas Instruments, Incorporated. All Rights Reserved.
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
*
================================================================================
*/
//
// File: image_cfg.h
//
// This file is also included in the config.bib. It's thereof very important that
// the preprocessor statements are limited to those understood by romimage.exe
// For example don't use #ifndef #endif but use #ifdef #else #endif, and keep the #define on 1 line only
//------------------------------------------------------------------------------
// EVM board 128 MB of SDRAM located physically at 0x80000000
//
#define DEVICE_RAM_PA 0x80000000
#define DEVICE_RAM_CA 0x80000000
#define DEVICE_RAM_SIZE 0x08000000
//------------------------------------------------------------------------------
//
// Define: IMAGE_SHARE_ARGS
//
// Following constants define location and maximal size of arguments shared
// between loader and kernel. For actual structure see args.h file.
//
#define IMAGE_SHARE_ARGS_CA 0x80000000
#define IMAGE_SHARE_ARGS_SIZE 0x00001000
//------------------------------------------------------------------------------
//
// Define: CPU_INFO_ADDR
//
// Following constants define location and maximal size of arguments shared
// between loader and kernel. For actual structure see args.h file.
//
#define CPU_INFO_ADDR_PA 0x80001000
#define CPU_INFO_ADDR_CA 0x80001000
#define CPU_INFO_ADDR_SIZE 0x00001000
//------------------------------------------------------------------------------
//
// Define: IMAGE_WINCE_CODE
//
// Following constants define Windows CE OS image layout.
//
#define IMAGE_WINCE_CODE_CA 0x80002000
#define IMAGE_WINCE_CODE_SIZE 0x02FFE000
#define IMAGE_WINCE_RAM_CA 0x0C000000
#define IMAGE_WINCE_RAM_SIZE 0x8F000000
#define IMAGE_WINCE_DISPLAY_CA 0x87000000
#define IMAGE_WINCE_DISPLAY_SIZE 0x01000000
#define IMAGE_WINCE_NOR_OFFSET 0x00060000
#define NAND_ROMOFFSET 0x40000000
#define NOR_ROMOFFSET 0x60000000
//------------------------------------------------------------------------------
//
// Define: IMAGE_XLDR_xxx
//
// Following constants define image layout for X-Loader. used to download/program the XLDR
// XLDR executes from SRAM. (MMU is not used in XLDR, so the address are physical here)
// NOTE : This is for flash XLDR. (XLDR SD is another matter)
#define IMAGE_XLDR_CODE_PA 0x40200000
#define IMAGE_XLDR_CODE_SIZE 0x00009000
#define IMAGE_XLDR_DATA_PA 0x40209000
#define IMAGE_XLDR_DATA_SIZE 0x00003000
#define IMAGE_XLDR_STACK_PA 0x4020F000
#define IMAGE_XLDR_STACK_SIZE 0x00000FFC
#define IMAGE_XLDR_NOR_OFFSET (0x00000000)
//------------------------------------------------------------------------------
//
// Define: IMAGE_EBOOT_xxx
//
// Following constants define EBOOT image layout.
//
#define IMAGE_EBOOT_CODE_CA 0x87E00000
#define IMAGE_EBOOT_CODE_SIZE 0x00040000
#define IMAGE_EBOOT_DATA_CA 0x87E80000
#define IMAGE_EBOOT_DATA_SIZE 0x00050000
#define IMAGE_EBOOT_NOR_OFFSET 0x00020000
#define IMAGE_EBOOT_CFG_NOR_OFFSET 0x00008000
//------------------------------------------------------------------------------
//
// Define: IMAGE_STARTUP_xxx
//
// Jump address XLDR uses to bring-up the device.
//
#define IMAGE_STARTUP_IMAGE_PA (IMAGE_EBOOT_CODE_CA - DEVICE_RAM_CA + DEVICE_RAM_PA)
#define IMAGE_STARTUP_IMAGE_CA (IMAGE_EBOOT_CODE_CA)
#define IMAGE_STARTUP_IMAGE_SIZE (IMAGE_EBOOT_CODE_SIZE)
//------------------------------------------------------------------------------
//
// Define: IMAGE_BOOTLOADER_xxx
//
// Following constants define bootloader information
//
#define IMAGE_XLDR_BOOTSEC_NAND_SIZE (4 * 128 * 1024) // Needs to be equal to four NAND flash blocks due to boot ROM requirements
#define IMAGE_EBOOT_BOOTSEC_NAND_SIZE IMAGE_EBOOT_CODE_SIZE // Needs to be a multiple of flash block size
#define IMAGE_BOOTLOADER_BITMAP_SIZE 0x00100000 // Needs to be a multiple of 128k, and minimum 480x640x3 (VGA)
#define IMAGE_BOOTLOADER_NAND_SIZE (IMAGE_XLDR_BOOTSEC_NAND_SIZE + IMAGE_EBOOT_BOOTSEC_NAND_SIZE + IMAGE_BOOTLOADER_BITMAP_SIZE)
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Define: IMAGE_DISPLAY_BUF_xxx
//
// Following constants define location and size of the display buffer
//
#define IMAGE_DISPLAY_BUF_PA IMAGE_WINCE_DISPLAY_CA
#define IMAGE_DISPLAY_BUF_SIZE 0x01000000
Feng Jian,
In your code the IMAGE_WINCE_RAM_CA(you set it to 0x0c000000), IMAGE_WINCE_RAM_SIZE and IMAGE_WINCE_DISPLAY_CA are not configured properly, corrected as follows in RED.
#define IMAGE_WINCE_CODE_CA 0x80002000
#define IMAGE_WINCE_CODE_SIZE 0x02FFE000
#define IMAGE_WINCE_RAM_CA 0x83000000
#define IMAGE_WINCE_RAM_SIZE 0x0C000000
#define IMAGE_WINCE_DISPLAY_CA 0x8F000000
#define IMAGE_WINCE_DISPLAY_SIZE 0x01000000
#define IMAGE_WINCE_NOR_OFFSET 0x00060000
Thanks,
Tao
Tao Zhang said:properly, corrected as follows in RED.
#define IMAGE_WINCE_CODE_CA 0x80002000
#define IMAGE_WINCE_CODE_SIZE 0x02FFE000
#define IMAGE_WINCE_RAM_CA 0x83000000
#define IMAGE_WINCE_RAM_SIZE 0x0C000000
#define IMAGE_WINCE_DISPLAY_CA 0x8F000000
I use two pieces of ddr(128MBytes, 16bits bus), and change above info. as below:
#define IMAGE_WINCE_CODE_CA 0x80002000
#define IMAGE_WINCE_CODE_SIZE 0x02FFE000
#define IMAGE_WINCE_RAM_CA 0x83000000
#define IMAGE_WINCE_RAM_SIZE 0x07000000
#define IMAGE_WINCE_DISPLAY_CA 0x8A000000
#define IMAGE_DISPLAY_BUF_PA 0x8A000000 // 0x87000000
#define IMAGE_DISPLAY_BUF_SIZE 0x04000000 // 64M
but I can't start my wince os , after load the wince image, and block,like this
-----------------------------------------------------------
[0]: Address=0x80002000 Length=0x01e20b10 Save=0x80002000
-----------------------------------------------------------
Download file type: 1
.........................................................................................................................................................................................................................rom_offset=0x0.
..ImageStart = 0x80002000, ImageLength = 0x1E20B10, LaunchAddr = 0x800110B8
Completed file(s):
-------------------------------------------------------------------------------
[0]: Address=0x80002000 Length=0x1E20B10 Name="" Target=RAM
ROMHDR at Address 80002044h
Launch Windows CE image by jumping to 0x800110b8...
Windows CE Kernel for ARM (Thumb Enabled) Built on Apr 5 2011 at 17:47:22
****Profiler Build****
---High Performance Frequency is 32768 hz---
Here the system block,the IMAGE_WINCE_RAM_SIZE must be keep continuous??
the attach is image_cfg.h,as reference.
thanks
Hi,
CODE (RAMIMAGE) and RAM section are not required to be continuous.
If CODE section and RAM section are continuous, then you can take advantage of "AUTOSIZE" option. Meaning, when the allocated CODE memory is not big enough to hold NK.bin, it will be automatically re-sized to use RAM section of the memory.
For you boot issue, I have a couple of pointers for you:
1. Double check if "OAL Retail Messages" is enabled from Eboot menu?
2. Do you use DISPLAY buffer in Eboot? If yes, is it overlapping with Eboot image? Can you change it to 0x8FE00000?
3. Please check how are your two piece of memory connected and which CSx signal is used? What is the physical base address for each piece, is addrtab_cfg.inc configured accordingly?
Thanks,
Tao
if you are using BSP 01.02.00, then AM3517 BSP uses the entire 256MB by default - you dont have to do anything.
-Madhvi
Elad,
Here are a few steps to start with:
1. First of all, you need to find out the phsical address range and timing parameters for the DDR2 RAM. Use these paratermeters configure GPMC regsiters in platform.c/bsp_def.h.
Add some code in XLDR or Eboot to make sure the memory is accessible.
2. Based on the phsical address range, modify addrtab_cfg.inc to map it to virtually address space.
3. Check image.h and config.bib , make sure there is no overlaps in your memory layout.
Thanks,
Tao