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AM5728: Separate EMIF I/O cells control

Marco Caldari
Intellectual 290 points
Part Number: AM5728

Hi everybody,

we use both EMIF1 and EMIF2 on the AM5728.

Signal integrity simulation was used to obtain the optimal setup for ODT, slew rate and output impedance for the pads of each of the 2 memory interfaces.

Different timing parameters can be copied from the EMIF tool to the related EMIF1 and EMIF2 structures, for example "struct emif_regsemif1_ddr3_532_mhz_1cs_2G" and "struct emif_regsemif2_ddr3_532_mhz_1cs_2G".

But, for each processor, it seems that there is a common structure for both EMIF1 and EMIF2 for the setup of I/O pads, for example "struct ctrl_ioregs ioregs_dra7xx_es1"; the AM5728 has separate configuration registers: CTRL_CORE_CONTROL_DDRCACH1_0 + CTRL_CORE_CONTROL_DDRCH1_x for EMIF1 and CTRL_CORE_CONTROL_DDRCACH2_0 + CTRL_CORE_CONTROL_DDRCH2_x for EMIF2.

Is this understanding correct?

Which is the right way to configure the I/O pads of EMIF1 independently from EMIF2?

Many thanks in advance for your support.

Regards,

Marco

  • 0
    TI__Guru* 87020 points

    Marco, if the 2 EMIFs have different settings for ODT, slew etc., or different timing parameters, it is best to generate a separate spreadsheet for each memory interface to get the proper configuration values for each EMIF.

    Regards,

    James

  • 0 in reply to JJD
    Intellectual 290 points

    Hi James,

    thank you for your reply.

    We took the opportunity to double-check the results of signal integrity simulations and eventually we were able to generate the same configuration (timing and I/O pads control) for both EMIF1 and EMIF2.

    Kind regards,

    Marco